From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1DA637D10A; Tue, 24 Mar 2026 01:57:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774317481; cv=none; b=RwFEdb9XH0BjENg6oYW4OeuvVnDz/FaPwN1dLI5lpKk5gT2NPvqbuuNvUMlLXv+X7YzmfTpY2gstOUhN0tHtBP6ZbY+cyflGZDX4dR/EkTbdVTMP3dBHtC4khHa5fCKRKJ0nnpMvKbL2g0Odu+nF8JhTXMDm2zhxKXRt20s016c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774317481; c=relaxed/simple; bh=wfCKSeLwH3NZDXYCpiWAto5KNoOjR+Aja8oWGr3EebM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tHTcsHRhte4Pw0KANSeCH42Bjc6RvuPhNc2f5ZTf5CBpLvRJureSR3Ajb7DFGcJ1aNaKGeNhTfkV0C8eto05H0bxmmNMoLEbIEWGLB9Rc6uXpkkcw05Ag4zf4OBDi8qeiP15Rg1v4Md07J/hzQy3j01UYVdWSmCntLuKJQ8sxMo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=gWBKNI9g; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="gWBKNI9g" X-UUID: dee5c80c272411f1a39cd589f645bc18-20260324 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=F4bQdtWr1UGDHgb8P4Qhggd4tq+ItN7H3PA0UGpnJWI=; b=gWBKNI9giv26mSDgqD4qqJ2d9bGiuP3+OKJ93WU0TwIRY8qEM2BzchAIqS/6DGKIH1vH9DjoLR9J+FPL+cRfSgiv4k7MwPeelAJw8PDk/gMzlrYXM0iZdQ3l0sMRH2LG4nviaej/P0FdocxZNTeDuOmrfhRGXhsHrpCvxMuWXe8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:a0066364-c7a0-4db5-b958-f815aeabda02,IP:0,U RL:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:20 X-CID-META: VersionHash:e7bac3a,CLOUDID:89bd0dd5-060f-4ecc-9ee0-121eeeb4a682,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:11|97|99|83|106|1,File:130,RT:0,Bulk:nil,QS:nil, BEC:-1,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: dee5c80c272411f1a39cd589f645bc18-20260324 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 26689475; Tue, 24 Mar 2026 09:57:53 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Tue, 24 Mar 2026 09:57:52 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Tue, 24 Mar 2026 09:57:51 +0800 From: Cyril Chao To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai CC: , , , , , Cyril Chao , , Darren Ye , Krzysztof Kozlowski , Cyril Chao Subject: [PATCH v8 07/10] ASoC: dt-bindings: mediatek,mt8196-afe: add audio AFE Date: Tue, 24 Mar 2026 09:56:48 +0800 Message-ID: <20260324015719.17543-8-Cyril.Chao@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260324015719.17543-1-Cyril.Chao@mediatek.com> References: <20260324015719.17543-1-Cyril.Chao@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N From: Darren Ye Add mt8196 audio AFE. Signed-off-by: Darren Ye Reviewed-by: Krzysztof Kozlowski Signed-off-by: Cyril Chao --- .../bindings/sound/mediatek,mt8196-afe.yaml | 113 ++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml new file mode 100644 index 000000000000..949f8622baf9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8196-afe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Audio Front End PCM controller for MT8196 + +maintainers: + - Darren Ye + +properties: + compatible: + const: mediatek,mt8196-afe + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: mux for audio intbus + - description: mux for audio engen1 + - description: mux for audio engen2 + - description: mux for audio h + - description: audio apll1 clock + - description: audio apll2 clock + - description: audio apll12 divide for i2sin0 + - description: audio apll12 divide for i2sin1 + - description: audio apll12 divide for fmi2s + - description: audio apll12 divide for tdmout mck + - description: audio apll12 divide for tdmout bck + - description: mux for adsp clock + + clock-names: + items: + - const: top_aud_intbus + - const: top_aud_eng1 + - const: top_aud_eng2 + - const: top_aud_h + - const: apll1 + - const: apll2 + - const: apll12_div_i2sin0 + - const: apll12_div_i2sin1 + - const: apll12_div_fmi2s + - const: apll12_div_tdmout_m + - const: apll12_div_tdmout_b + - const: top_adsp + +required: + - compatible + - reg + - interrupts + - memory-region + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + afe@1a110000 { + compatible = "mediatek,mt8196-afe"; + reg = <0 0x1a110000 0 0x9000>; + interrupts = ; + memory-region = <&afe_dma_mem_reserved>; + power-domains = <&scpsys 14>; //MT8196_POWER_DOMAIN_AUDIO + pinctrl-names = "default"; + pinctrl-0 = <&aud_pins_default>; + clocks = <&vlp_cksys_clk 40>, //CLK_VLP_CK_AUD_INTBUS_SEL + <&vlp_cksys_clk 38>, //CLK_VLP_CK_AUD_ENGEN1_SEL + <&vlp_cksys_clk 39>, //CLK_VLP_CK_AUD_ENGEN2_SEL + <&vlp_cksys_clk 37>, //CLK_VLP_CK_AUDIO_H_SEL + <&vlp_cksys_clk 0>, //CLK_VLP_CK_VLP_APLL1 + <&vlp_cksys_clk 1>, //CLK_VLP_CK_VLP_APLL2 + <&cksys_clk 80>, //CLK_CK_APLL12_CK_DIV_I2SIN0 + <&cksys_clk 81>, //CLK_CK_APLL12_CK_DIV_I2SIN1 + <&cksys_clk 92>, //CLK_CK_APLL12_CK_DIV_FMI2S + <&cksys_clk 93>, //CLK_CK_APLL12_CK_DIV_TDMOUT_M + <&cksys_clk 94>, //CLK_CK_APLL12_CK_DIV_TDMOUT_B + <&cksys_clk 45>; //CLK_CK_ADSP_SEL + clock-names = "top_aud_intbus", + "top_aud_eng1", + "top_aud_eng2", + "top_aud_h", + "apll1", + "apll2", + "apll12_div_i2sin0", + "apll12_div_i2sin1", + "apll12_div_fmi2s", + "apll12_div_tdmout_m", + "apll12_div_tdmout_b", + "top_adsp"; + }; + }; + +... -- 2.45.2