Re: [PATCH v2 4/5] PCI: tegra: Add Tegra264 support

[kernel test robot <lkp@intel.com>]

Hi Thierry,

kernel test robot noticed the following build errors:

[auto build test ERROR on tegra/for-next]
[also build test ERROR on next-20260323]
[cannot apply to pci/next pci/for-linus drm-tegra/drm/tegra/for-next linus/master v7.0-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Thierry-Reding/soc-tegra-Update-BPMP-ABI-header/20260323-093336
base:   https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
patch link:    https://lore.kernel.org/r/20260320225443.2571920-5-thierry.reding%40kernel.org
patch subject: [PATCH v2 4/5] PCI: tegra: Add Tegra264 support
config: riscv-allyesconfig (https://download.01.org/0day-ci/archive/20260324/202603241635.M39jGMQX-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260324/202603241635.M39jGMQX-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603241635.M39jGMQX-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/pci/controller/pcie-tegra264.c:302:16: error: use of undeclared identifier 'PCIE_LINK_WAIT_US_MIN'
                   usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
                                ^
>> drivers/pci/controller/pcie-tegra264.c:302:39: error: use of undeclared identifier 'PCIE_LINK_WAIT_US_MAX'
                   usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
                                                       ^
   drivers/pci/controller/pcie-tegra264.c:392:16: error: call to undeclared function 'tegra_bpmp_get_with_id'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
                   pcie->bpmp = tegra_bpmp_get_with_id(dev, &pcie->ctl_id);
                                ^
   drivers/pci/controller/pcie-tegra264.c:392:14: error: incompatible integer to pointer conversion assigning to 'struct tegra_bpmp *' from 'int' [-Wint-conversion]
                   pcie->bpmp = tegra_bpmp_get_with_id(dev, &pcie->ctl_id);
                              ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   4 errors generated.


vim +/PCIE_LINK_WAIT_US_MIN +302 drivers/pci/controller/pcie-tegra264.c

   278	
   279	static void tegra264_pcie_init(struct tegra264_pcie *pcie)
   280	{
   281		enum pci_bus_speed speed;
   282		unsigned int i;
   283		u32 value;
   284	
   285		/* bring the link out of reset */
   286		value = readl(pcie->xtl + XTL_RC_MGMT_PERST_CONTROL);
   287		value |= XTL_RC_MGMT_PERST_CONTROL_PERST_O_N;
   288		writel(value, pcie->xtl + XTL_RC_MGMT_PERST_CONTROL);
   289	
   290		if (!tegra_is_silicon()) {
   291			dev_info(pcie->dev,
   292				 "skipping link state for PCIe #%u in simulation\n",
   293				 pcie->ctl_id);
   294			pcie->link_up = true;
   295			return;
   296		}
   297	
   298		for (i = 0; i < PCIE_LINK_WAIT_MAX_RETRIES; i++) {
   299			if (tegra264_pcie_link_up(pcie, NULL))
   300				break;
   301	
 > 302			usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
   303		}
   304	
   305		if (tegra264_pcie_link_up(pcie, &speed)) {
   306			/* Per PCIe r5.0, 6.6.1 wait for 100ms after DLL up */
   307			msleep(PCIE_RESET_CONFIG_WAIT_MS);
   308	
   309			dev_info(pcie->dev, "PCIe #%u link is up (speed: %s)\n",
   310				 pcie->ctl_id, pci_speed_string(speed));
   311			tegra264_pcie_icc_set(pcie);
   312			pcie->link_up = true;
   313		} else {
   314			dev_info(pcie->dev, "PCIe #%u link is down\n", pcie->ctl_id);
   315	
   316			value = readl(pcie->xtl + XTL_RC_MGMT_CLOCK_CONTROL);
   317	
   318			/*
   319			 * Set link state only when link fails and no hot-plug feature
   320			 * is present.
   321			 */
   322			if ((value & XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT) == 0) {
   323				dev_info(pcie->dev,
   324					 "PCIe #%u link is down and not hotplug-capable, turning off\n",
   325					 pcie->ctl_id);
   326				tegra264_pcie_bpmp_set_rp_state(pcie);
   327				pcie->link_up = false;
   328			} else {
   329				pcie->link_up = true;
   330			}
   331		}
   332	}
   333	

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