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This chip is currently modeled only as a fixed regulator (vcc3v3_pi6c_03), with no clock output representation. The PI6C20100 is a clock generator, not a power supply. Model it properly as a gated-fixed-clock, following the pattern established for the Rock 5 ITX and other boards with similar PCIe clock buffer chips. The gated-fixed-clock node references the regulator as its vdd-supply, allowing the regulator to be enabled on demand. Remove the regulator-always-on and regulator-boot-on properties from vcc3v3_pi6c_03 since the clock framework will manage the regulator lifecycle via vdd-supply. The pcie3x2 node is updated to include the pipe and reference clocks, matching the approach used in rk3588-rock-5-itx.dts. Assisted-by: Claude:claude-3-opus Signed-off-by: Midgy BALON --- Changes since v5: - Drop "(100MHz)" from clock node comment, already in clock-frequency (Jonas) - Drop redundant comment before vcc3v3_pi6c_03 (Jonas) - Remove regulator-always-on and regulator-boot-on from vcc3v3_pi6c_03 (Jonas) - Drop Reviewed-by (patch has functional changes since v3 review) Changes since v4: - Fix From: line to match Signed-off-by (Heiko) Changes since v3 [1]: - Add Reviewed-by from Shawn Lin Changes since v2 [2]: - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn) - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks override (Shawn, referencing David's patch [3]) Changes since v1 [4]: - Drop phy-supply approach entirely (Jonas, Shawn) - Model PI6C20100 as gated-fixed-clock instead - Wire reference clock to pcie3x2 controller - Follow pattern from rk3588-rock-5-itx.dts [1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/ [2] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/ [3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1 [4] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/ .../boot/dts/rockchip/rk3568-rock-3b.dts | 20 ++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts index 3d0c1ccfa..d7d85b090 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts @@ -56,7 +56,15 @@ led-0 { }; }; - /* pi6c pcie clock generator */ + /* PI6C20100 PCIe reference clock buffer */ + pcie30_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_03>; + }; + vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { compatible = "regulator-fixed"; enable-active-high; @@ -64,8 +72,6 @@ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { pinctrl-names = "default"; pinctrl-0 = <&pcie_pwren_h>; regulator-name = "vcc3v3_pi6c_03"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <10000>; @@ -545,6 +551,14 @@ &pcie30phy { }; &pcie3x2 { + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>, + <&pcie30_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "pipe", "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; -- 2.30.2