From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (unknown [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC7EB3C552D; Mon, 30 Mar 2026 10:48:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.187.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867702; cv=none; b=ipdeU9BNr1B9VqEwhb7AnhnsTRPX2FYZiADpTLUby1Pah9/kNgssV5laFvzXCvNRlMGd0ETBfcjJ73ogCiHr+na/+TJcK9JYvQ8IDoU5M3tTJtBGdC88y+bOOvr/uERLkUcYNNODfAhsKnuATwDtkRaCn2U8/LT+hLI8skc5AE0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867702; c=relaxed/simple; bh=CQ87WG7tB0NGFgqYnwUzrD65BoyJsudzvJu0vnidgbQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=reiVeLeE7D7T0czZSd694vQbp0CrX/z3qfvKdfoiyrPKcoLtdxlKuTX7QHYszbS2ODLdfF0bpcx2wc6l2rNRNYXL6mdOp9GoSNLWCyy6Sb+wlEiTAhllqPk4QmNvijJ/OyDd1UQoXnKenIHncu2Oz/XINUlv1s54FMW3sfdy4zk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.187.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 62UATE7s040024; Mon, 30 Mar 2026 18:29:14 +0800 (+08) (envelope-from minachou@andestech.com) Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62UASEsn038230; Mon, 30 Mar 2026 18:28:14 +0800 (+08) (envelope-from minachou@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 30 Mar 2026 18:28:14 +0800 From: Hui Min Mina Chou To: , , , , , , , , , , , , , , , CC: , , , "Hui Min Mina Chou" Subject: [PATCH 4/7] cache: andes_llcache: centralize cache ops and use native WBINVAL Date: Mon, 30 Mar 2026 18:27:21 +0800 Message-ID: <20260330102724.1012470-5-minachou@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330102724.1012470-1-minachou@andestech.com> References: <20260330102724.1012470-1-minachou@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 62UATE7s040024 Introduce andes_cpu_cache_operation() to centralize address translation, alignment, and IRQ handling, removing the redundant wrappers andes_cpu_dcache_wb_range and andes_cpu_dcache_inval_range. This refactoring includes the following refinements: - Consolidates address translation, boundary alignment, and IRQ handling (local_irq_save/restore) into the central function. - Make IRQ handling per cache line instead of across the entire cache operation. - Cleans up redundant intermediate wrapper functions (andes_cpu_dcache_wb_range, andes_cpu_dcache_inval_range). - wback_inv was chaining wback + inv separately; use the hardware's native WBINVAL CCTL instead, which does both in one shot. Signed-off-by: Alex Chun-Ju Lin Signed-off-by: Hui Min Mina Chou --- drivers/cache/andes_llcache.c | 63 ++++++++++++----------------------- 1 file changed, 21 insertions(+), 42 deletions(-) diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c index 57f666bc537a..0efa6e9c80bd 100644 --- a/drivers/cache/andes_llcache.c +++ b/drivers/cache/andes_llcache.c @@ -69,21 +69,29 @@ static inline uint32_t andes_cpu_llc_get_cctl_status(void) return readl_relaxed(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0); } -static void andes_cpu_cache_operation(unsigned long start, unsigned long end, - unsigned int l1_op, unsigned int llc_op) +static void andes_cpu_cache_operation(phys_addr_t paddr, size_t size, + unsigned int l1_op, unsigned int llc_op) { unsigned long line_size = andes_priv.andes_cache_line_size; void __iomem *base = andes_priv.llc_base; + unsigned long start = (unsigned long)phys_to_virt(paddr); + unsigned long end = start + size; + unsigned long flags; unsigned long pa; int mhartid = 0; + start = ALIGN_DOWN(start, line_size); + end = ALIGN(end, line_size); + if (IS_ENABLED(CONFIG_SMP)) mhartid = cpuid_to_hartid_map(get_cpu()); else mhartid = cpuid_to_hartid_map(0); mb(); /* complete earlier memory accesses before the cache flush */ - while (end > start) { + for (; start < end; start += line_size) { + local_irq_save(flags); + csr_write(CSR_UCCTLBEGINADDR, start); csr_write(CSR_UCCTLCOMMAND, l1_op); @@ -95,7 +103,7 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end, ANDES_LLC_CCTL_STATUS_IDLE) ; - start += line_size; + local_irq_restore(flags); } mb(); /* issue later memory accesses after the cache flush */ @@ -103,60 +111,31 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end, put_cpu(); } -/* Write-back L1 and LLC entry */ -static inline void andes_cpu_dcache_wb_range(unsigned long start, unsigned long end) -{ - andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_WB, - ANDES_LLC_CCTL_PA_WB); -} - -/* Invalidate the L1 and LLC entry */ -static inline void andes_cpu_dcache_inval_range(unsigned long start, unsigned long end) -{ - andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_INVAL, - ANDES_LLC_CCTL_PA_INVAL); -} - static void andes_dma_cache_inv(phys_addr_t paddr, size_t size) { - unsigned long start = (unsigned long)phys_to_virt(paddr); - unsigned long end = start + size; - unsigned long line_size = andes_priv.andes_cache_line_size; - unsigned long flags; - if (unlikely(!size)) return; - start = ALIGN_DOWN(start, line_size); - end = ALIGN(end, line_size); - - local_irq_save(flags); - andes_cpu_dcache_inval_range(start, end); - local_irq_restore(flags); + andes_cpu_cache_operation(paddr, size, ANDES_L1D_CCTL_VA_INVAL, + ANDES_LLC_CCTL_PA_INVAL); } static void andes_dma_cache_wback(phys_addr_t paddr, size_t size) { - unsigned long start = (unsigned long)phys_to_virt(paddr); - unsigned long end = start + size; - unsigned long line_size = andes_priv.andes_cache_line_size; - unsigned long flags; - if (unlikely(!size)) return; - start = ALIGN_DOWN(start, line_size); - end = ALIGN(end, line_size); - - local_irq_save(flags); - andes_cpu_dcache_wb_range(start, end); - local_irq_restore(flags); + andes_cpu_cache_operation(paddr, size, ANDES_L1D_CCTL_VA_WB, + ANDES_LLC_CCTL_PA_WB); } static void andes_dma_cache_wback_inv(phys_addr_t paddr, size_t size) { - andes_dma_cache_wback(paddr, size); - andes_dma_cache_inv(paddr, size); + if (unlikely(!size)) + return; + + andes_cpu_cache_operation(paddr, size, ANDES_L1D_CCTL_VA_WBINVAL, + ANDES_LLC_CCTL_PA_WBINVAL); } static int andes_get_llc_line_size(struct device_node *np) -- 2.34.1