From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF0DC1FF5E3; Mon, 30 Mar 2026 10:29:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.187.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774866580; cv=none; b=dkKRe5UpuA7B2jiQBc6n7alV4zFWVXG5x6kQU86ogvuOhTNR5GK3Ixk29bDK8wqW/r7xKzY8Jpzf0trkTqOTK5WaW3jAUj/wS3kdxfV1Md+1rIOz7VftskvJBC5kdTTi1y8OaGR1Y1zcBP6iAgdWA1gmF7H9VkY6i3Pn5f+YQCE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774866580; c=relaxed/simple; bh=xR4/eiW2jwE62sTUaUNq6rB16VdY5+2Jv/gBv7tkuoc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RLMpaQe2sUJlSgouvjnkA1MLycIVGcBC4SIZ6kheASP0C8c2U61+nkRLNpTYNWj6uyuhprn6lNK3JjPqU5t4TIBeyKxSMZVjEsIh+Bg7TmMl2B0SmJuKNuwCDPRFosdak9vtvE2msz9O9Ap8moRyZHvdPX8ao76LcA86+xtdaZo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.187.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62UASI1F038289; Mon, 30 Mar 2026 18:28:18 +0800 (+08) (envelope-from minachou@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 30 Mar 2026 18:28:18 +0800 From: Hui Min Mina Chou To: , , , , , , , , , , , , , , , CC: , , , "Hui Min Mina Chou" Subject: [PATCH 6/7] dts: riscv: update cache compatible strings to LLC Date: Mon, 30 Mar 2026 18:27:23 +0800 Message-ID: <20260330102724.1012470-7-minachou@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330102724.1012470-1-minachou@andestech.com> References: <20260330102724.1012470-1-minachou@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 62UASI1F038289 Update the cache driver compatible strings from ax45mp-cache to llcache for both Qilai and RZ/Five platforms. This follows the Andes cache driver refactoring to use more generic Last Level Cache (LLC) naming. Signed-off-by: Hui Min Mina Chou --- arch/riscv/boot/dts/andes/qilai.dtsi | 4 ++-- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi index de3de32f8c39..a7436cbf6f69 100644 --- a/arch/riscv/boot/dts/andes/qilai.dtsi +++ b/arch/riscv/boot/dts/andes/qilai.dtsi @@ -137,8 +137,8 @@ plmt: timer@100000 { }; l2_cache: cache-controller@200000 { - compatible = "andestech,qilai-ax45mp-cache", - "andestech,ax45mp-cache", "cache"; + compatible = "andestech,qilai-llcache", + "andestech,llcache", "cache"; reg = <0x0 0x00200000 0x0 0x100000>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; cache-line-size = <64>; diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index 571de3cafa82..83a5d4d41f8e 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -144,7 +144,7 @@ plic: interrupt-controller@12c00000 { }; l2cache: cache-controller@13400000 { - compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache", + compatible = "renesas,r9a07g043f-llcache", "andestech,llcache", "cache"; reg = <0x0 0x13400000 0x0 0x100000>; interrupts = ; -- 2.34.1