From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B86CE3BF677; Tue, 31 Mar 2026 07:31:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774942317; cv=none; b=uHMWPalyJYVjiB3i0dPiyPhnd3ICxZwequWwqQkw7n8VYihkg3QFCModcQCVs+XEqfFEQ564ZvZiRmg+ckdXVvnTh8tqIa61/K315ofzEJFcG3igpVlgkWkCHUmBDvKQbeleYd00qdwPHds/4qSZiywlN0jFfpfYx7ejetNdiQY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774942317; c=relaxed/simple; bh=j/lCVMm5Ghps1IlCQohPFeP1bg8qFP/vfQXBUgF2UOk=; h=From:Subject:Date:Message-ID:MIME-Version:Content-Type:To:CC; b=n2E8V9aQ20zVQjwOXnruy7/kxWlcyunGIT6lXZ8nIoTHG7reqU1l39MLBTGx7TNNQt6y7fAV49geGZiiSoALn74qNeU1gUTbsE8JnVrzEwx3Pc6+qGCKe9WKKzmPik1+btX/AyBy6gp3J6XQAOF7DKcPAydMEemPuoAI4HdF9aA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 31 Mar 2026 15:31:46 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 31 Mar 2026 15:31:46 +0800 From: Billy Tsai Subject: [PATCH v5 0/3] pinctrl: aspeed: Add AST2700 SoC0 support Date: Tue, 31 Mar 2026 15:31:15 +0800 Message-ID: <20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAEN4y2kC/2XOSw6CMBSF4a2Qji25hRaLI/dhCClwkZvwSluJh LB3CwMHOvwH58vZmENL6Ngt2pjFhRxNYwh1iVjdmfGJnJrQLIFEiUQo/pqdt2iGcqax9rbnuhW 5alow+VWxMJsttvQ+yUcRurXTwH0XNl8IcpACUgki1jrRVy54RX2/lt4Zuhs3IzYe6y6up+EgO 3J+sut5cpEHfDAZpJD9/1kkB24aidpUupI6/wWLfd8/v27IgfgAAAA= X-Change-ID: 20251215-upstream_pinctrl-8f195df0a975 To: Lee Jones , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Joel Stanley" , Andrew Jeffery , "Linus Walleij" , Billy Tsai , "Bartosz Golaszewski" , Ryan Chen CC: Andrew Jeffery , , , , , , , X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774942306; l=4186; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=j/lCVMm5Ghps1IlCQohPFeP1bg8qFP/vfQXBUgF2UOk=; b=aOXMWn/+I2zqHn2S2EwLGvr8ir5DNMlD6PgJZepWEs/vXfsC4L+kWgAWP1OHArvvuGxfKb733 xD7C1dHhGcoDg0e9exp7M/jZIyYUzKv1446iEQRgmDv6hJ0sE0R26uG X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= AST2700 is composed of two interconnected SoC instances, each providing its own pin control hardware. This series introduces bindings describing the AST2700 pinctrl architecture and adds pinctrl driver support for the SoC0 instance. The bindings document the AST2700 dual-SoC design and follow common pinctrl conventions, while the SoC0 driver implementation builds upon the existing ASPEED pinctrl infrastructure. --- Changes in v5: - Complete the AST2700 SCU0 binding and disallow child nodes that are not relevant for the hardware (p2a-control and smp-memram). - Add examples for both the AST2700 SCU0 binding and the pinctrl binding, ensuring they are valid against the schema. - Rework the pinctrl binding example to be self-contained and independent of the SCU binding. - Reorder the binding patches so the pinctrl binding is introduced before the SCU binding update, allowing the SCU example to be added cleanly. - Adjust the binding accordingly to restrict drive-strength to the supported values. - Update the drive-strength table to match hardware-defined values. - Link to v4: https://lore.kernel.org/r/20260306-upstream_pinctrl-v4-0-ad4e8ab8b489@aspeedtech.com Changes in v4: - Rename series title to "pinctrl: aspeed: Add AST2700 SoC0 support" to make it specific to SoC0. - Remove unnecessary SCU example from bindings. - Fix Makefile newline to avoid patch warning. - Make pinctrl data structures const and align with existing Aspeed drivers. - Sort the arrays and enums alphabetically. - Minor cleanups for consistency, no functional changes. - Link to v3: https://lore.kernel.org/r/20260120-upstream_pinctrl-v3-0-868fbf8413b5@aspeedtech.com Changes in v3: dt-bindings: pinctrl: aspeed: AST2700 pinctrl improvements - Improved binding descriptions for SoC0 and SoC1 to better explain the AST2700 dual-SoC architecture with independent pin control blocks - Switched from additionalProperties to patternProperties using the '-state$' suffix to restrict child node naming - Removed per-binding examples based on review feedback - Added additionalProperties: false at the top level for stricter schema validation - Dropped the aspeed,ast2700-soc1-pinctrl binding, as the SoC1 pinctrl registers follow a regular layout and can be described using an existing generic pinctrl binding - Updated the function and group enum lists to match the definitions used by the AST2700 pinctrl driver dt-bindings: mfd: aspeed: Add AST2700 SCU example with pinctrl - Added a complete AST2700 SCU0 example demonstrating pinctrl integration - Example covers both pin function/group configuration and pin drive-strength settings - Updated child node naming to use the '-state' suffix, following common pinctrl conventions pinctrl: aspeed: AST2700 SoC0 driver improvements - Refactored pin and signal declarations to use common ASPEED pinmux macros (SIG_EXPR_LIST_DECL_SEMG, SIG_EXPR_LIST_DECL_SESG, PIN_DECL_*) - Added SCU010 register definition for hardware strap control - Reworked code structure to better align with existing ASPEED pinctrl drivers - Link to v2: https://lore.kernel.org/r/20250904103401.88287-1-billy_tsai@aspeedtech.com Changes in v2: - Update pinctrl aspeed binding files. - Update the commit message for pinctrl binding patch. - Link to v1: https://lore.kernel.org/r/20250829073030.2749482-1-billy_tsai@aspeedtech.com --- Billy Tsai (3): dt-bindings: pinctrl: Add aspeed,ast2700-soc0-pinctrl dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0 pinctrl: aspeed: Add AST2700 SoC0 support .../bindings/mfd/aspeed,ast2x00-scu.yaml | 117 ++++ .../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 161 +++++ drivers/pinctrl/aspeed/Kconfig | 9 + drivers/pinctrl/aspeed/Makefile | 1 + drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c | 710 +++++++++++++++++++++ 5 files changed, 998 insertions(+) --- base-commit: af4e9ef3d78420feb8fe58cd9a1ab80c501b3c08 change-id: 20251215-upstream_pinctrl-8f195df0a975 Best regards, -- Billy Tsai