[PATCH v1 0/2] Add DeepComputing FML13V05 board dts

[PATCH v1 0/2] Add DeepComputing FML13V05 board dts

[Sandie Cao]

This series updates Device Tree related files to introduce the
FML13V05 board from DeepComputing, which incorporates a Spacemit
K3 SoC.  This board is designed for use on the Framework Laptop 13
Chassis, which has (Framework) SKU FRANHQ0001.

The series is based on riscv-dt-for-next.

sandiecao (2):
  dt-bindings: riscv: spacemit: add deepcomputing,fml13v05
  riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

 .../devicetree/bindings/riscv/spacemit.yaml   |  1 +
 arch/riscv/boot/dts/spacemit/Makefile         |  1 +
 .../spacemit/k3-deepcomputing-fml13v05.dts    | 28 +++++++++++++++++++
 3 files changed, 30 insertions(+)
 create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts


base-commit: 4a1739c30fc66a59450c1f78923f94607e786882
-- 
2.43.0

[PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

[Sandie Cao]

From: sandiecao <sandie.cao@deepcomputing.io>

Document the compatible string for the Deepcomputing fml13v05.
It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework
Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
 Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml
index b958b94a924d..af8030242bdc 100644
--- a/Documentation/devicetree/bindings/riscv/spacemit.yaml
+++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml
@@ -29,6 +29,7 @@ properties:
           - const: spacemit,k1
       - items:
           - enum:
+              - deepcomputing,fml13v05
               - spacemit,k3-pico-itx
           - const: spacemit,k3
 
-- 
2.43.0

[PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

[Sandie Cao]

From: sandiecao <sandie.cao@deepcomputing.io>

The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
which has (Framework) SKU FRANHQ0001.

The FML13V05 board features:
- SpacemiT K3 RISC-V SoC
- LPDDR5 16GB or 32GB
- eMMC 32GB ~128GB (Optional)
- UFS 3.1 256G (Optional)
- QSPI Flash
- MicroSD Slot
- PCIe-based Wi-Fi
- 4 USB-C Ports
 - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
 - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
 - Port 3 & 4: USB 3.2 Gen 1

This minimal device tree enables booting into a serial console with UART
output.

Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
 arch/riscv/boot/dts/spacemit/Makefile         |  1 +
 .../spacemit/k3-deepcomputing-fml13v05.dts    | 28 +++++++++++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts

diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
index 7e2b87702571..acb993c452ba 100644
--- a/arch/riscv/boot/dts/spacemit/Makefile
+++ b/arch/riscv/boot/dts/spacemit/Makefile
@@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
+dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
new file mode 100644
index 000000000000..2343ae3acc2d
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 DeepComputing (HK) Limited
+ */
+
+#include "k3.dtsi"
+
+/ {
+	model = "DeepComputing FML13V05";
+	compatible = "deepcomputing,fml13v05", "spacemit,k3";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	memory@100000000 {
+		device_type = "memory";
+		reg = <0x1 0x00000000 0x4 0x00000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.43.0

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

[Troy Mitchell]

On Tue Mar 31, 2026 at 11:46 AM CST, Sandie Cao wrote:
> From: sandiecao <sandie.cao@deepcomputing.io>
>
> The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
> SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
> which has (Framework) SKU FRANHQ0001.
>
> The FML13V05 board features:
> - SpacemiT K3 RISC-V SoC
> - LPDDR5 16GB or 32GB
> - eMMC 32GB ~128GB (Optional)
> - UFS 3.1 256G (Optional)
> - QSPI Flash
> - MicroSD Slot
> - PCIe-based Wi-Fi
> - 4 USB-C Ports
>  - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
>  - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
>  - Port 3 & 4: USB 3.2 Gen 1
>
> This minimal device tree enables booting into a serial console with UART
> output.
>
> Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>

Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

[Yixun Lan]

Hi Sandie,
On 11:45 Tue 31 Mar     , Sandie Cao wrote:
> From: sandiecao <sandie.cao@deepcomputing.io>

Can you use more formal format for your name? which,
Sandie Cao <sandie.cao@deepcomputing.io>

> 
> Document the compatible string for the Deepcomputing fml13v05.
> It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework
> Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.
> 
> Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
same here
> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
>  Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml
> index b958b94a924d..af8030242bdc 100644
> --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml
> +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml
> @@ -29,6 +29,7 @@ properties:
>            - const: spacemit,k1
>        - items:
>            - enum:
> +              - deepcomputing,fml13v05
>                - spacemit,k3-pico-itx
>            - const: spacemit,k3
>  
> -- 
> 2.43.0

-- 
Yixun Lan (dlan)

Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

[曹珊珊]

> From: "Yixun Lan"<dlan@kernel.org>
> Date:  Tue, Mar 31, 2026, 14:03
> Subject:  Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05
> To: "Sandie Cao"<sandie.cao@deepcomputing.io>
> Cc: "Conor Dooley"<conor+dt@kernel.org>, "Emil Renner Berthing"<kernel@esmil.dk>, "Rob Herring"<robh@kernel.org>, "Krzysztof Kozlowski"<krzk+dt@kernel.org>, "Paul Walmsley"<paul.walmsley@sifive.com>, "Palmer Dabbelt"<palmer@dabbelt.com>, "Albert Ou"<aou@eecs.berkeley.edu>, "Heinrich Schuchardt"<heinrich.schuchardt@canonical.com>, "Troy Mitchell"<troy.mitchell@linux.spacemit.com>, "Michael Opdenacker"<michael.opdenacker@rootcommit.com>, "Guodong Xu"<guodong@riscstar.com>, "Hendrik Hamerlinck"<hendrik.hamerlinck@hammernet.be>, "Yangyu Chen"<cyy@cyyself.name>, <spacemit@lists.linux.dev>, <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
> Hi Sandie,
> On 11:45 Tue 31 Mar     , Sandie Cao wrote:
> > From: sandiecao <sandie.cao@deepcomputing.io>
> 
> Can you use more formal format for your name? which,
> Sandie Cao <sandie.cao@deepcomputing.io>

OK. Got it. I will fix it in next version.
Sandie

> 
> > 
> > Document the compatible string for the Deepcomputing fml13v05.
> > It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework
> > Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.
> > 
> > Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
> same here
> > Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> > ---
> >  Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml
> > index b958b94a924d..af8030242bdc 100644
> > --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml
> > @@ -29,6 +29,7 @@ properties:
> >            - const: spacemit,k1
> >        - items:
> >            - enum:
> > +              - deepcomputing,fml13v05
> >                - spacemit,k3-pico-itx
> >            - const: spacemit,k3
> >  
> > -- 
> > 2.43.0
> 
> -- 
> Yixun Lan (dlan)
> 

Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

[Troy Mitchell]

On Tue Mar 31, 2026 at 2:15 PM CST, 曹珊珊 wrote:
>
>> From: "Yixun Lan"<dlan@kernel.org>
>> Date:  Tue, Mar 31, 2026, 14:03
>> Subject:  Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05
>> To: "Sandie Cao"<sandie.cao@deepcomputing.io>
>> Cc: "Conor Dooley"<conor+dt@kernel.org>, "Emil Renner Berthing"<kernel@esmil.dk>, "Rob Herring"<robh@kernel.org>, "Krzysztof Kozlowski"<krzk+dt@kernel.org>, "Paul Walmsley"<paul.walmsley@sifive.com>, "Palmer Dabbelt"<palmer@dabbelt.com>, "Albert Ou"<aou@eecs.berkeley.edu>, "Heinrich Schuchardt"<heinrich.schuchardt@canonical.com>, "Troy Mitchell"<troy.mitchell@linux.spacemit.com>, "Michael Opdenacker"<michael.opdenacker@rootcommit.com>, "Guodong Xu"<guodong@riscstar.com>, "Hendrik Hamerlinck"<hendrik.hamerlinck@hammernet.be>, "Yangyu Chen"<cyy@cyyself.name>, <spacemit@lists.linux.dev>, <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
I'm just confused as to why this appeared in the body.

                          - Troy

Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

[曹珊珊]

> On Tue Mar 31, 2026 at 2:15 PM CST, 曹珊珊 wrote:
> >
> >> From: "Yixun Lan"<dlan@kernel.org>
> >> Date:  Tue, Mar 31, 2026, 14:03
> >> Subject:  Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05
> >> To: "Sandie Cao"<sandie.cao@deepcomputing.io>
> >> Cc: "Conor Dooley"<conor+dt@kernel.org>, "Emil Renner Berthing"<kernel@esmil.dk>, "Rob Herring"<robh@kernel.org>, "Krzysztof Kozlowski"<krzk+dt@kernel.org>, "Paul Walmsley"<paul.walmsley@sifive.com>, "Palmer Dabbelt"<palmer@dabbelt.com>, "Albert Ou"<aou@eecs.berkeley.edu>, "Heinrich Schuchardt"<heinrich.schuchardt@canonical.com>, "Troy Mitchell"<troy.mitchell@linux.spacemit.com>, "Michael Opdenacker"<michael.opdenacker@rootcommit.com>, "Guodong Xu"<guodong@riscstar.com>, "Hendrik Hamerlinck"<hendrik.hamerlinck@hammernet.be>, "Yangyu Chen"<cyy@cyyself.name>, <spacemit@lists.linux.dev>, <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
> I'm just confused as to why this appeared in the body.
> 
>                           - Troy
> 

This was the format of my email sender. 
I correct it now. 
Thanks.
Sandie

[PATCH v2 0/2] Add DeepComputing FML13V05 board dts

[Sandie Cao]

This series updates Device Tree related files to introduce the
FML13V05 board from DeepComputing, which incorporates a Spacemit
K3 SoC.  This board is designed for use on the Framework Laptop 13
Chassis, which has (Framework) SKU FRANHQ0001.

The series is based on riscv-dt-for-next.

v2:
- Patch 1:
   Use formal format user name.
- Patch 2:
   Use formal format user name.
   Add Reviewed-by from Troy Mitchell.

Link to v1: https://lore.kernel.org/all/20260331034423.67142-1-sandie.cao@deepcomputing.io/

Sandie Cao (2):
  dt-bindings: riscv: spacemit: add deepcomputing,fml13v05
  riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

 .../devicetree/bindings/riscv/spacemit.yaml   |  1 +
 arch/riscv/boot/dts/spacemit/Makefile         |  1 +
 .../spacemit/k3-deepcomputing-fml13v05.dts    | 28 +++++++++++++++++++
 3 files changed, 30 insertions(+)
 create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts


base-commit: 4a1739c30fc66a59450c1f78923f94607e786882
-- 
2.43.0

[PATCH v2 0/2] Add DeepComputing FML13V05 board dts

[Sandie Cao]

This series updates Device Tree related files to introduce the
FML13V05 board from DeepComputing, which incorporates a Spacemit
K3 SoC.  This board is designed for use on the Framework Laptop 13
Chassis, which has (Framework) SKU FRANHQ0001.

The series is based on riscv-dt-for-next.

v2:
- Patch 1:
   Use formal format user name.
- Patch 2:
   Use formal format user name.
   Add Reviewed-by from Troy Mitchell.

Link to v1: https://lore.kernel.org/all/20260331034423.67142-1-sandie.cao@deepcomputing.io/

Sandie Cao (2):
  dt-bindings: riscv: spacemit: add deepcomputing,fml13v05
  riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

 .../devicetree/bindings/riscv/spacemit.yaml   |  1 +
 arch/riscv/boot/dts/spacemit/Makefile         |  1 +
 .../spacemit/k3-deepcomputing-fml13v05.dts    | 28 +++++++++++++++++++
 3 files changed, 30 insertions(+)
 create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts


base-commit: 4a1739c30fc66a59450c1f78923f94607e786882
-- 
2.43.0

Re: [PATCH v2 0/2] Add DeepComputing FML13V05 board dts

[Troy Mitchell]

Hi Sandie,

On Tue Mar 31, 2026 at 3:11 PM CST, Sandie Cao wrote:
> This series updates Device Tree related files to introduce the
> FML13V05 board from DeepComputing, which incorporates a Spacemit
> K3 SoC.  This board is designed for use on the Framework Laptop 13
> Chassis, which has (Framework) SKU FRANHQ0001.
>
> The series is based on riscv-dt-for-next.
>
> v2:
> - Patch 1:
>    Use formal format user name.
> - Patch 2:
>    Use formal format user name.
>    Add Reviewed-by from Troy Mitchell.
>
> Link to v1: https://lore.kernel.org/all/20260331034423.67142-1-sandie.cao@deepcomputing.io/
Please slow down a bit. Sending a v2 immediately after a single review doesn't
give others (especially those in different time zones) a chance to look at v1.
It's better to wait a day or two to collect more feedback before sending a new iteration

                        - Troy

Re: [PATCH v2 0/2] Add DeepComputing FML13V05 board dts

[曹珊珊]

> Hi Sandie,
> 
> On Tue Mar 31, 2026 at 3:11 PM CST, Sandie Cao wrote:
> > This series updates Device Tree related files to introduce the
> > FML13V05 board from DeepComputing, which incorporates a Spacemit
> > K3 SoC.  This board is designed for use on the Framework Laptop 13
> > Chassis, which has (Framework) SKU FRANHQ0001.
> >
> > The series is based on riscv-dt-for-next.
> >
> > v2:
> > - Patch 1:
> >    Use formal format user name.
> > - Patch 2:
> >    Use formal format user name.
> >    Add Reviewed-by from Troy Mitchell.
> >
> > Link to v1: https://lore.kernel.org/all/20260331034423.67142-1-sandie.cao@deepcomputing.io/
> Please slow down a bit. Sending a v2 immediately after a single review doesn't
> give others (especially those in different time zones) a chance to look at v1.
> It's better to wait a day or two to collect more feedback before sending a new iteration
> 
>                         - Troy
> 

Got it. 
Thanks a lot.
Sandie

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

[Yixun Lan]

Hi Sandie, 

On 11:46 Tue 31 Mar     , Sandie Cao wrote:
> From: sandiecao <sandie.cao@deepcomputing.io>
> 
> The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
> SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
> which has (Framework) SKU FRANHQ0001.
> 
> The FML13V05 board features:
> - SpacemiT K3 RISC-V SoC
> - LPDDR5 16GB or 32GB
> - eMMC 32GB ~128GB (Optional)
> - UFS 3.1 256G (Optional)
> - QSPI Flash
> - MicroSD Slot
> - PCIe-based Wi-Fi
> - 4 USB-C Ports
>  - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
>  - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
>  - Port 3 & 4: USB 3.2 Gen 1
> 
> This minimal device tree enables booting into a serial console with UART
> output.
> 
> Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
should put your own signed-off at the end.

> ---
>  arch/riscv/boot/dts/spacemit/Makefile         |  1 +
>  .../spacemit/k3-deepcomputing-fml13v05.dts    | 28 +++++++++++++++++++
>  2 files changed, 29 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
> 
> diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
> index 7e2b87702571..acb993c452ba 100644
> --- a/arch/riscv/boot/dts/spacemit/Makefile
> +++ b/arch/riscv/boot/dts/spacemit/Makefile
> @@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
>  dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
>  dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
>  dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
> +dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb
>  dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
> diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
> new file mode 100644
> index 000000000000..2343ae3acc2d
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2024 DeepComputing (HK) Limited
should cover current year, which is 2026 now..

> + */
> +
> +#include "k3.dtsi"
> +
> +/ {
> +	model = "DeepComputing FML13V05";
> +	compatible = "deepcomputing,fml13v05", "spacemit,k3";
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0";
> +	};
> +
> +	memory@100000000 {
> +		device_type = "memory";
> +		reg = <0x1 0x00000000 0x4 0x00000000>;
> +	};
> +};
> +
> +&uart0 {
Can you also add pinctrl data explicitly?

> +	status = "okay";
> +};
> -- 
> 2.43.0

-- 
Yixun Lan (dlan)

Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

[Krzysztof Kozlowski]

On Tue, Mar 31, 2026 at 11:45:39AM +0800, Sandie Cao wrote:
> From: sandiecao <sandie.cao@deepcomputing.io>
> 
> Document the compatible string for the Deepcomputing fml13v05.
> It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework
> Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.
> 
> Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>

Name feels clsoe to login name and even login name has a '.' in the
middle, so a bit tricky to judge. Please clarify your name.

> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

Is the review coming from some internal sysstems or downstream forks? If
so, does the review checks the same things as upstream is expected,
including known identity in DCO?


Best regards,
Krzysztof

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

[曹珊珊]

Hi Lan,

> From: "Yixun Lan"<dlan@kernel.org>
> Hi Sandie, 
> 
> On 11:46 Tue 31 Mar     , Sandie Cao wrote:
> > From: sandiecao <sandie.cao@deepcomputing.io>
> > 
> > The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
> > SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
> > which has (Framework) SKU FRANHQ0001.
> > 
> > The FML13V05 board features:
> > - SpacemiT K3 RISC-V SoC
> > - LPDDR5 16GB or 32GB
> > - eMMC 32GB ~128GB (Optional)
> > - UFS 3.1 256G (Optional)
> > - QSPI Flash
> > - MicroSD Slot
> > - PCIe-based Wi-Fi
> > - 4 USB-C Ports
> >  - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
> >  - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
> >  - Port 3 & 4: USB 3.2 Gen 1
> > 
> > This minimal device tree enables booting into a serial console with UART
> > output.
> > 
> > Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
> > Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> should put your own signed-off at the end.
> 
> > ---
> >  arch/riscv/boot/dts/spacemit/Makefile         |  1 +
> >  .../spacemit/k3-deepcomputing-fml13v05.dts    | 28 +++++++++++++++++++
> >  2 files changed, 29 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
> > 
> > diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
> > index 7e2b87702571..acb993c452ba 100644
> > --- a/arch/riscv/boot/dts/spacemit/Makefile
> > +++ b/arch/riscv/boot/dts/spacemit/Makefile
> > @@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
> >  dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
> >  dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
> >  dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
> > +dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb
> >  dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
> > diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
> > new file mode 100644
> > index 000000000000..2343ae3acc2d
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
> > @@ -0,0 +1,28 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2024 DeepComputing (HK) Limited
> should cover current year, which is 2026 now..
> 
> > + */
> > +
> > +#include "k3.dtsi"
> > +
> > +/ {
> > +        model = "DeepComputing FML13V05";
> > +        compatible = "deepcomputing,fml13v05", "spacemit,k3";
> > +
> > +        aliases {
> > +                serial0 = &uart0;
> > +        };
> > +
> > +        chosen {
> > +                stdout-path = "serial0";
> > +        };
> > +
> > +        memory@100000000 {
> > +                device_type = "memory";
> > +                reg = <0x1 0x00000000 0x4 0x00000000>;
> > +        };
> > +};
> > +
> > +&uart0 {
> Can you also add pinctrl data explicitly?

To avoid conflict,  the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit. 
Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch. 
Sandie

> 
> > +        status = "okay";
> > +};
> > -- 
> > 2.43.0
> 
> -- 
> Yixun Lan (dlan)
> 

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

[Troy Mitchell]

On Wed Apr 1, 2026 at 2:10 PM CST, 曹珊珊 wrote:
> Hi Lan,
>
>> From: "Yixun Lan"<dlan@kernel.org>
>> Hi Sandie, 
>> 
>> On 11:46 Tue 31 Mar     , Sandie Cao wrote:
>> > From: sandiecao <sandie.cao@deepcomputing.io>
>> > 
>> > The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
>> > SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
>> > which has (Framework) SKU FRANHQ0001.
>> > 
>> > The FML13V05 board features:
>> > - SpacemiT K3 RISC-V SoC
>> > - LPDDR5 16GB or 32GB
>> > - eMMC 32GB ~128GB (Optional)
>> > - UFS 3.1 256G (Optional)
>> > - QSPI Flash
>> > - MicroSD Slot
>> > - PCIe-based Wi-Fi
>> > - 4 USB-C Ports
>> >  - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
>> >  - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
>> >  - Port 3 & 4: USB 3.2 Gen 1
>> > 
>> > This minimal device tree enables booting into a serial console with UART
>> > output.
>> > 
>> > Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
>> > Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
>> > +&uart0 {
>> Can you also add pinctrl data explicitly?
>
> To avoid conflict,  the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit. 
> Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch. 
> Sandie
I think you don't understand what Yixun said.
You should add pinctrl properties here like:
pinctrl-0 = xxx;
pinctrl-names = "default";

While the bootloader is expected to initialize the UART pins, explicitly adding the pinctrl properties
ensures hardware state consistency.

                                      - Troy

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

[曹珊珊]

Hi Troy,

> From: "Troy Mitchell"<troy.mitchell@linux.spacemit.com>
> Date:  Wed, Apr 1, 2026, 14:42

> On Wed Apr 1, 2026 at 2:10 PM CST, 曹珊珊 wrote:
> > Hi Lan,
> >
> >> From: "Yixun Lan"<dlan@kernel.org>
> >> Hi Sandie, 
> >> 
> >> On 11:46 Tue 31 Mar     , Sandie Cao wrote:
> >> > From: sandiecao <sandie.cao@deepcomputing.io>
> >> > 
> >> > The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
> >> > SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
> >> > which has (Framework) SKU FRANHQ0001.
> >> > 
> >> > The FML13V05 board features:
> >> > - SpacemiT K3 RISC-V SoC
> >> > - LPDDR5 16GB or 32GB
> >> > - eMMC 32GB ~128GB (Optional)
> >> > - UFS 3.1 256G (Optional)
> >> > - QSPI Flash
> >> > - MicroSD Slot
> >> > - PCIe-based Wi-Fi
> >> > - 4 USB-C Ports
> >> >  - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
> >> >  - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
> >> >  - Port 3 & 4: USB 3.2 Gen 1
> >> > 
> >> > This minimal device tree enables booting into a serial console with UART
> >> > output.
> >> > 
> >> > Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
> >> > Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> >> > +&uart0 {
> >> Can you also add pinctrl data explicitly?
> >
> > To avoid conflict,  the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit. 
> > Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch. 
> > Sandie
> I think you don't understand what Yixun said.
> You should add pinctrl properties here like:
> pinctrl-0 = xxx;
> pinctrl-names = "default";
> 
> While the bootloader is expected to initialize the UART pins, explicitly adding the pinctrl properties
> ensures hardware state consistency.
> 
>                                       - Troy
> 

Yes, I know this.
If I add 
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_0_cfg>;
Then also need to add
&pinctrl {
        uart0_0_cfg: uart0-0-cfg {
                uart0-0-pins {
                        pinmux = <K3_PADCONF(149, 2)>,        /* uart0 tx */
                                 <K3_PADCONF(150, 2)>;        /* uart0 rx */

                        bias-pull-up;                        /* normal pull-up */
                        drive-strength = <25>;                /* DS8 */
                };
        };
};
But this part is common, it should be defined in common pinctrl table "k3-pinctrl.dtsi". And this part hasn't comed to Upstream.
If I add it currently,  When k3-pinctrl.dtsi is accepted by Upstream, we need to remove it again.
So we just empty it for simple.
Sandie

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

[Troy Mitchell]

On Wed Apr 1, 2026 at 3:38 PM CST, 曹珊珊 wrote:
> Hi Troy,
>
>> From: "Troy Mitchell"<troy.mitchell@linux.spacemit.com>
>> Date:  Wed, Apr 1, 2026, 14:42
>
>> On Wed Apr 1, 2026 at 2:10 PM CST, 曹珊珊 wrote:
>> > Hi Lan,
>> >
>> >> From: "Yixun Lan"<dlan@kernel.org>
>> >> Hi Sandie, 
>> >> 
>> >> On 11:46 Tue 31 Mar     , Sandie Cao wrote:
>> >> > From: sandiecao <sandie.cao@deepcomputing.io>
>> >> > 
>> >> > The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
>> >> > SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
>> >> > which has (Framework) SKU FRANHQ0001.
>> >> > 
>> >> > The FML13V05 board features:
>> >> > - SpacemiT K3 RISC-V SoC
>> >> > - LPDDR5 16GB or 32GB
>> >> > - eMMC 32GB ~128GB (Optional)
>> >> > - UFS 3.1 256G (Optional)
>> >> > - QSPI Flash
>> >> > - MicroSD Slot
>> >> > - PCIe-based Wi-Fi
>> >> > - 4 USB-C Ports
>> >> >  - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
>> >> >  - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
>> >> >  - Port 3 & 4: USB 3.2 Gen 1
>> >> > 
>> >> > This minimal device tree enables booting into a serial console with UART
>> >> > output.
>> >> > 
>> >> > Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
>> >> > Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
>> >> > +&uart0 {
>> >> Can you also add pinctrl data explicitly?
>> >
>> > To avoid conflict,  the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit. 
>> > Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch. 
>> > Sandie
>> I think you don't understand what Yixun said.
>> You should add pinctrl properties here like:
>> pinctrl-0 = xxx;
>> pinctrl-names = "default";
>> 
>> While the bootloader is expected to initialize the UART pins, explicitly adding the pinctrl properties
>> ensures hardware state consistency.
>> 
>>                                       - Troy
>> 
>
> Yes, I know this.
> If I add 
>         pinctrl-names = "default";
>         pinctrl-0 = <&uart0_0_cfg>;
> Then also need to add
> &pinctrl {
>         uart0_0_cfg: uart0-0-cfg {
>                 uart0-0-pins {
>                         pinmux = <K3_PADCONF(149, 2)>,        /* uart0 tx */
>                                  <K3_PADCONF(150, 2)>;        /* uart0 rx */
>
>                         bias-pull-up;                        /* normal pull-up */
>                         drive-strength = <25>;                /* DS8 */
>                 };
>         };
> };
> But this part is common, it should be defined in common pinctrl table "k3-pinctrl.dtsi". And this part hasn't comed to Upstream.
This line exceeds 100 characters

> If I add it currently,  When k3-pinctrl.dtsi is accepted by Upstream, we need to remove it again.
> So we just empty it for simple.
No, It looks like your base commit is wrong.
It has been merged here [1] that what you said.

By the way, I noticed that the name in your 'From' header for this reply doesn't match the one in
your patch submission. It would be better to keep them consistent to avoid any confusion for the
maintainers/reviewers regarding the authorship of the response.

Link:
https://lore.kernel.org/all/177340832523.17050.323606076175943251.b4-ty@kernel.org/ [1]


                                    - Troy

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

[Sandie Cao]

Hi Troy,

> From: "Troy Mitchell"<troy.mitchell@linux.spacemit.com>
> Date:  Wed, Apr 1, 2026, 15:55

> On Wed Apr 1, 2026 at 3:38 PM CST, 曹珊珊 wrote:
> > Hi Troy,
> >
> >> From: "Troy Mitchell"<troy.mitchell@linux.spacemit.com>
> >> Date:  Wed, Apr 1, 2026, 14:42
> >
> >> On Wed Apr 1, 2026 at 2:10 PM CST, 曹珊珊 wrote:
> >> > Hi Lan,
> >> >
> >> >> From: "Yixun Lan"<dlan@kernel.org>
> >> >> Hi Sandie, 
> >> >> 
> >> >> On 11:46 Tue 31 Mar     , Sandie Cao wrote:
> >> >> > From: sandiecao <sandie.cao@deepcomputing.io>
> >> >> > 
> >> >> > The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
> >> >> > SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
> >> >> > which has (Framework) SKU FRANHQ0001.
> >> >> > 
> >> >> > The FML13V05 board features:
> >> >> > - SpacemiT K3 RISC-V SoC
> >> >> > - LPDDR5 16GB or 32GB
> >> >> > - eMMC 32GB ~128GB (Optional)
> >> >> > - UFS 3.1 256G (Optional)
> >> >> > - QSPI Flash
> >> >> > - MicroSD Slot
> >> >> > - PCIe-based Wi-Fi
> >> >> > - 4 USB-C Ports
> >> >> >  - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
> >> >> >  - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
> >> >> >  - Port 3 & 4: USB 3.2 Gen 1
> >> >> > 
> >> >> > This minimal device tree enables booting into a serial console with UART
> >> >> > output.
> >> >> > 
> >> >> > Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
> >> >> > Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> >> >> > +&uart0 {
> >> >> Can you also add pinctrl data explicitly?
> >> >
> >> > To avoid conflict,  the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit. 
> >> > Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch. 
> >> > Sandie
> >> I think you don't understand what Yixun said.
> >> You should add pinctrl properties here like:
> >> pinctrl-0 = xxx;
> >> pinctrl-names = "default";
> >> 
> >> While the bootloader is expected to initialize the UART pins, explicitly adding the pinctrl properties
> >> ensures hardware state consistency.
> >> 
> >>                                       - Troy
> >> 
> >
> > Yes, I know this.
> > If I add 
> >         pinctrl-names = "default";
> >         pinctrl-0 = <&uart0_0_cfg>;
> > Then also need to add
> > &pinctrl {
> >         uart0_0_cfg: uart0-0-cfg {
> >                 uart0-0-pins {
> >                         pinmux = <K3_PADCONF(149, 2)>,        /* uart0 tx */
> >                                  <K3_PADCONF(150, 2)>;        /* uart0 rx */
> >
> >                         bias-pull-up;                        /* normal pull-up */
> >                         drive-strength = <25>;                /* DS8 */
> >                 };
> >         };
> > };
> > But this part is common, it should be defined in common pinctrl table "k3-pinctrl.dtsi". And this part hasn't comed to Upstream.
> This line exceeds 100 characters
> 
> > If I add it currently,  When k3-pinctrl.dtsi is accepted by Upstream, we need to remove it again.
> > So we just empty it for simple.
> No, It looks like your base commit is wrong.
> It has been merged here [1] that what you said.
> 

Got it. I will use https://github.com/spacemit-com/linux/tree/k1/dt-for-next  to rebase my patch.


> By the way, I noticed that the name in your 'From' header for this reply doesn't match the one in
> your patch submission. It would be better to keep them consistent to avoid any confusion for the
> maintainers/reviewers regarding the authorship of the response.
> 

Already fixed it.
Thanks a lot.
Sandie


> Link:
> https://lore.kernel.org/all/177340832523.17050.323606076175943251.b4-ty@kernel.org/ [1]
> 
> 
>                                     - Troy
>