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Tue, 31 Mar 2026 03:23:21 -0700 From: Akhil R To: Vinod Koul , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , "Jonathan Hunter" , Laxman Dewangan , Philipp Zabel , , , , CC: Akhil R Subject: [PATCH v6 00/10] Add GPCDMA support in Tegra264 Date: Tue, 31 Mar 2026 15:52:53 +0530 Message-ID: <20260331102303.33181-1-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37B:EE_|LV2PR12MB5751:EE_ X-MS-Office365-Filtering-Correlation-Id: f9c479fe-634c-406b-7079-08de8f0f92c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|82310400026|1800799024|921020|18002099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sCfcIZ2Mvf+ud22pgUVzJhJ6JNIiVPoUPsGQ5tf8aDheegT/U5GiFK87tqpde/vVexdtIW9PQZ0x3xBEdo1aV6hDeAQpQqLdxhoABXCVBiFp3pIzzXYtkXVUE86/h2rDYa+LQu1xwhZ/4amvcoYfCgfX27jx7bGPwDAVo3FRKFTabt2wHctG7Llcsk4zTehN7cD/2nBHZEoTF1Cz/Fhw/J1yT7VGlD/AjaWEDvsg/rKZM7HnkG2rr6AIXKsxNiOusu8pss/P0T6Rx6haxLSQ4NguBYvZnr6r9TnwMp2XbcrzkqvzyVPsMTH6vy69Zg6KB411osR1KQpsG0qzOW4g2BPn+lM8CmLVpq+Xx+VcJ3p96lH3NSP0PoGrFRoIKH7LwEaUTH+2iWuekj5yPcWyqoBSmuRWPRKeeq74aR4VwiKRX+opsXe1oKmwQXIqd3nM X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Mar 2026 10:23:38.1123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9c479fe-634c-406b-7079-08de8f0f92c1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5751 This series adds support for GPCDMA in Tegra264 with additional support for separate stream ID for each channel. Tegra264 GPCDMA controller has changes in the register offsets and uses 41-bit addressing for memory. Add changes in the tegra186-gpc-dma driver to support these. v5->v6: - Replace dev_err() with dev_err_probe() in the probe function for fixed return values also. v4->v5: - Use dev_err_probe() when returning error from the probe function. - Remove tegra194 and tegra234 compatible from the reset 'if' condition in the bindings as suggested in v2 (which I missed). v3->v4: - Split device tree changes to two patches. - Reordered patches to have fixes first. - Added fixes tag to dt-bindings and device tree changes. v2->v3: - Add description for iommu-map property and update commit descriptions. - Use enum for compatible string instead of const. - Remove unused registers from struct tegra_dma_channel_regs. - Use devm_of_dma_controller_register() to register the DMA controller. - Remove return value check for mask setting in the driver as the bitmask value is always greater than 32. v1->v2: - Fix dt_bindings_check warnings - Drop fallback compatible "nvidia,tegra186-gpcdma" from Tegra264 DT - Use dma_addr_t for sg_req src/dst fields and drop separate high_add variable and check for the addr_bits only when programming the registers. - Update address width to 39 bits for Tegra234 and before since the SMMU supports only up to 39 bits till Tegra234. - Add a patch to do managed DMA controller registration. - Describe the second iteration in the probe. - Update commit descriptions. Akhil R (10): dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional arm64: tegra: Remove fallback compatible for GPCDMA dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property dmaengine: tegra: Make reset control optional dmaengine: tegra: Use struct for register offsets dmaengine: tegra: Support address width > 39 bits dmaengine: tegra: Use managed DMA controller registration dmaengine: tegra: Use iommu-map for stream ID dmaengine: tegra: Add Tegra264 support arm64: tegra: Enable GPCDMA in Tegra264 and add iommu-map .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 32 +- .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 4 + arch/arm64/boot/dts/nvidia/tegra264.dtsi | 3 +- drivers/dma/tegra186-gpc-dma.c | 429 +++++++++++------- 4 files changed, 284 insertions(+), 184 deletions(-) -- 2.50.1