[PATCH v2 0/7] PCI: intel-gw: Fixes to make the driver working again

[PATCH v2 0/7] PCI: intel-gw: Fixes to make the driver working again

[Florian Eckert]

This patch series fixes the 'intel-gw' driver to work again with the
current pcie framework. The following changes are:

* Move interrupt 'enable' to its own function to improve readability,
  and add additinal register writes just as the Maxlinear kernel does in
  their SDK.
* Enable clock for the PHY before PHY init call.
* Add missing 'start_link' callback that was added to the PCIe dwc
  framework.
* Read ATU base assignment from the DTS rather than specifying it in the
  source of the driver.
* Remove unused preprocessor define.
* Mark driver as orphaned as the maitainer's email no longer works

Signed-off-by: Florian Eckert <fe@dev.tdt.de>
---
Changes in v2:
- Added additional information to the commit descriptions
- Add additional patch to mark driver as orphaned as the maintainer's
  email no longer works.
- Fix wrong error path for enable clock before phy init.
- Add new patch to update the devicetree documentation for the 'atu'
  resource
- Add additional recipients responsible for documenting the dervicetree
  bindings.
- Link to v1: https://lore.kernel.org/r/20260317-pcie-intel-gw-v1-0-7fe13726ad4f@dev.tdt.de

---
Florian Eckert (7):
      PCI: intel-gw: Remove unused define
      PCI: intel-gw: Move interrupt enable to own function
      PCI: intel-gw: Enable clock before phy init
      PCI: intel-gw: Add start_link callback function
      PCI: intel-gw: Remove atu base assignment
      dt-bindings: PCI: intel,lgm-pcie: Make atu resource mandatory
      MAINTAINERS: Remove bouncing intel-gw maintainer

 .../devicetree/bindings/pci/intel-gw-pcie.yaml     |  5 ++-
 MAINTAINERS                                        |  3 +-
 drivers/pci/controller/dwc/pcie-intel-gw.c         | 49 ++++++++++++----------
 3 files changed, 31 insertions(+), 26 deletions(-)
---
base-commit: f338e77383789c0cae23ca3d48adcc5e9e137e3c
change-id: 20260317-pcie-intel-gw-50902113f9e1

Best regards,
-- 
Florian Eckert <fe@dev.tdt.de>

[PATCH v2 1/7] PCI: intel-gw: Remove unused define

[Florian Eckert]

The C preprocessor define 'PCIE_APP_INTX_OFST' is not used in the sources
and can therefore be deleted.

Signed-off-by: Florian Eckert <fe@dev.tdt.de>
---
 drivers/pci/controller/dwc/pcie-intel-gw.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index c21906eced61896c8a8307dbd6b72d229f9a5c5f..80d1607c46cbbb1e274b37a0bb9377a877678f5d 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -47,7 +47,6 @@
 #define PCIE_APP_IRN_INTD		BIT(16)
 #define PCIE_APP_IRN_MSG_LTR		BIT(18)
 #define PCIE_APP_IRN_SYS_ERR_RC		BIT(29)
-#define PCIE_APP_INTX_OFST		12
 
 #define PCIE_APP_IRN_INT \
 	(PCIE_APP_IRN_AER_REPORT | PCIE_APP_IRN_PME | \

-- 
2.47.3

[PATCH v2 2/7] PCI: intel-gw: Move interrupt enable to own function

[Florian Eckert]

To improve the readability of the code, move the interrupt enable
instructions to a separate function. That is already done for the disable
interrupt instruction.

In addtion, all pending interrupts are cleared and disabled, just as this
is done in the disable function 'intel_pcie_core_irq_disable()'. After
that, all relevant interrupts are enabled again. The 'PCIE_APP_IRNEN'
definition contains all the relevant interrupts that are of interest.

This change is also done in the Maxlinear SDK [1]. As I unfortunately
don’t have any documentation for this IP core, I suspect that the
intention is to set the IP core for interrupt handling to a specific
state. Perhaps the problem was that the IP core did not reinitialize the
interrupt register properly after a power cycle.

In my view, it can’t do any harm to switch the interrupt off and then on
again to set them to a specific state.

[1] https://github.com/maxlinear/linux/blob/updk_9.1.90/drivers/pci/controller/dwc/pcie-intel-gw.c#L431

Signed-off-by: Florian Eckert <fe@dev.tdt.de>
---
 drivers/pci/controller/dwc/pcie-intel-gw.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 80d1607c46cbbb1e274b37a0bb9377a877678f5d..e88b8243cc41c607c39e4d58c4dcd8c8c082e8b0 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -195,6 +195,13 @@ static void intel_pcie_device_rst_deassert(struct intel_pcie *pcie)
 	gpiod_set_value_cansleep(pcie->reset_gpio, 0);
 }
 
+static void intel_pcie_core_irq_enable(struct intel_pcie *pcie)
+{
+	pcie_app_wr(pcie, PCIE_APP_IRNEN, 0);
+	pcie_app_wr(pcie, PCIE_APP_IRNCR, PCIE_APP_IRN_INT);
+	pcie_app_wr(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT);
+}
+
 static void intel_pcie_core_irq_disable(struct intel_pcie *pcie)
 {
 	pcie_app_wr(pcie, PCIE_APP_IRNEN, 0);
@@ -316,9 +323,7 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
 	if (ret)
 		goto app_init_err;
 
-	/* Enable integrated interrupts */
-	pcie_app_wr_mask(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT,
-			 PCIE_APP_IRN_INT);
+	intel_pcie_core_irq_enable(pcie);
 
 	return 0;
 

-- 
2.47.3

[PATCH v2 3/7] PCI: intel-gw: Enable clock before phy init

[Florian Eckert]

To ensure that the boot sequence is correct, the dwc pcie core clock must
be switched on before phy init call [1]. This changes are based on patched
kernel sources of the MaxLinear SDK.

[1] https://github.com/maxlinear/linux/blob/updk_9.1.90/drivers/pci/controller/dwc/pcie-intel-gw.c#L544

Signed-off-by: Florian Eckert <fe@dev.tdt.de>
---
 drivers/pci/controller/dwc/pcie-intel-gw.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index e88b8243cc41c607c39e4d58c4dcd8c8c082e8b0..6d9499d954674a26a74bff56b7fb5759767424c0 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -291,13 +291,9 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
 
 	intel_pcie_core_rst_assert(pcie);
 	intel_pcie_device_rst_assert(pcie);
-
-	ret = phy_init(pcie->phy);
-	if (ret)
-		return ret;
-
 	intel_pcie_core_rst_deassert(pcie);
 
+	/* Controller clock must be provided earlier than PHY */
 	ret = clk_prepare_enable(pcie->core_clk);
 	if (ret) {
 		dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret);
@@ -306,13 +302,17 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
 
 	pci->atu_base = pci->dbi_base + 0xC0000;
 
+	ret = phy_init(pcie->phy);
+	if (ret)
+		goto phy_err;
+
 	intel_pcie_ltssm_disable(pcie);
 	intel_pcie_link_setup(pcie);
 	intel_pcie_init_n_fts(pci);
 
 	ret = dw_pcie_setup_rc(&pci->pp);
 	if (ret)
-		goto app_init_err;
+		goto err;
 
 	dw_pcie_upconfig_setup(pci);
 
@@ -321,17 +321,18 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
 
 	ret = dw_pcie_wait_for_link(pci);
 	if (ret)
-		goto app_init_err;
+		goto err;
 
 	intel_pcie_core_irq_enable(pcie);
 
 	return 0;
 
-app_init_err:
+err:
+	phy_exit(pcie->phy);
+phy_err:
 	clk_disable_unprepare(pcie->core_clk);
 clk_err:
 	intel_pcie_core_rst_assert(pcie);
-	phy_exit(pcie->phy);
 
 	return ret;
 }

-- 
2.47.3

[PATCH v2 4/7] PCI: intel-gw: Add start_link callback function

[Florian Eckert]

The pcie-intel-gw driver has no start_link callback function. This commit
adds the missing callback function so that the driver works again and does
not abort with the following error messages during probing.

[    2.512015] intel-gw-pcie d1000000.pcie: host bridge /soc/pcie@d1000000 ranges:
[    2.517868] intel-gw-pcie d1000000.pcie:      MEM 0x00dc000000..0x00ddffffff -> 0x00dc000000
[    2.528450] intel-combo-phy d0c00000.combo-phy: Set combo mode: combophy[1]: mode: PCIe single lane mode
[    2.551619] intel-gw-pcie d1000000.pcie: No outbound iATU found
[    2.556060] intel-gw-pcie d1000000.pcie: Cannot initialize host
[    2.561901] intel-gw-pcie d1000000.pcie: probe with driver intel-gw-pcie failed with error -22
[    2.571041] intel-gw-pcie c1100000.pcie: host bridge /soc/pcie@c1100000 ranges:
[    2.577736] intel-gw-pcie c1100000.pcie:      MEM 0x00ce000000..0x00cfffffff -> 0x00ce000000
[    2.588299] intel-combo-phy c0c00000.combo-phy: Set combo mode: combophy[3]: mode: PCIe single lane mode
[    2.611471] intel-gw-pcie c1100000.pcie: No outbound iATU found
[    2.615934] intel-gw-pcie c1100000.pcie: Cannot initialize host
[    2.621759] intel-gw-pcie c1100000.pcie: probe with driver intel-gw-pcie failed with error -22

Fixes: c5097b9869a1 ("Revert "PCI: dwc: Wait for link up only if link is started"")
Fixes: da56a1bfbab5 ("PCI: dwc: Wait for link up only if link is started")
Signed-off-by: Florian Eckert <fe@dev.tdt.de>
---
 drivers/pci/controller/dwc/pcie-intel-gw.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 6d9499d954674a26a74bff56b7fb5759767424c0..24c463781f1e31d5617a5ff81bdbce563ed5a1d0 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -284,6 +284,16 @@ static void intel_pcie_turn_off(struct intel_pcie *pcie)
 	pcie_rc_cfg_wr_mask(pcie, PCI_COMMAND, PCI_COMMAND_MEMORY, 0);
 }
 
+static int intel_pcie_start_link(struct dw_pcie *pci)
+{
+	struct intel_pcie *pcie = dev_get_drvdata(pci->dev);
+
+	intel_pcie_device_rst_deassert(pcie);
+	intel_pcie_ltssm_enable(pcie);
+
+	return 0;
+}
+
 static int intel_pcie_host_setup(struct intel_pcie *pcie)
 {
 	int ret;
@@ -310,19 +320,8 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
 	intel_pcie_link_setup(pcie);
 	intel_pcie_init_n_fts(pci);
 
-	ret = dw_pcie_setup_rc(&pci->pp);
-	if (ret)
-		goto err;
-
 	dw_pcie_upconfig_setup(pci);
 
-	intel_pcie_device_rst_deassert(pcie);
-	intel_pcie_ltssm_enable(pcie);
-
-	ret = dw_pcie_wait_for_link(pci);
-	if (ret)
-		goto err;
-
 	intel_pcie_core_irq_enable(pcie);
 
 	return 0;
@@ -386,6 +385,7 @@ static int intel_pcie_rc_init(struct dw_pcie_rp *pp)
 }
 
 static const struct dw_pcie_ops intel_pcie_ops = {
+	.start_link = intel_pcie_start_link,
 };
 
 static const struct dw_pcie_host_ops intel_pcie_dw_ops = {

-- 
2.47.3

[PATCH v2 5/7] PCI: intel-gw: Remove atu base assignment

[Florian Eckert]

If no ATU resource is defined in the DTS, the default value is 0x300000[1].
This is set during probing in the function 'dw_pcie_get_resources()'[2].
The driver overwrites this again when its init callback is called in its
'intel_pcie_host_setup()' [3] function. This is because the value here is
'0xC0000' rather than '0x300000'. This callback is called by the dwc core
via 'pp->ops->init' [4].

function callstack:
intel_pcie_probe()
  dw_pcie_host_init()
    dw_pcie_host_get_resources()
      dw_pcie_get_resources() [2]
    pp->ops->init = intel_pcie_rc_init()
                      intel_pcie_host_setup() [3]

As backwards compatibility is not an issue here [5], the value for the ATU
resource is moved to the DTS and is therefore loaded by the dwc core. It
is therefore no longer necessary to overwrite the pci->atu_base address in
the init callback. The DTS must be modified so that the additional resource
is loaded correctly by the DWC core.

[1] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller/dwc/pcie-designware.h#L292
[2] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller/dwc/pcie-designware.c#L150
[3] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller/dwc/pcie-intel-gw.c#L301
[4] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller/dwc/pcie-designware-host.c#L589
[5] https://lore.kernel.org/all/BY3PR19MB507667CE7531D863E1E5F8AEBDD82@BY3PR19MB5076.namprd19.prod.outlook.com/

Signed-off-by: Florian Eckert <fe@dev.tdt.de>
---
 drivers/pci/controller/dwc/pcie-intel-gw.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 24c463781f1e31d5617a5ff81bdbce563ed5a1d0..f41b64ac48d5c05e6b0e5b14c3e0cd7a4c407d16 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -310,8 +310,6 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
 		goto clk_err;
 	}
 
-	pci->atu_base = pci->dbi_base + 0xC0000;
-
 	ret = phy_init(pcie->phy);
 	if (ret)
 		goto phy_err;

-- 
2.47.3

[PATCH v2 6/7] dt-bindings: PCI: intel,lgm-pcie: Make atu resource mandatory

[Florian Eckert]

The ATU information is already set in the dwc core if it is specified in
the DTS. The driver uses its own value here [1]. This information is
hardware specific and should therefore be maintained in the DTS rather
than in the source.

Backwards compatibility is not an issue here [5], as the driver is
exclusively used by Maxlinear.

Old DTS entry for PCIe:

reg = <0xd1000000 0x1000>,
      <0xd3000000 0x20000>,
      <0xd0c41000.0x1000>;
reg-names = "dbi", "config", "app";

New DTS entry for PCIe:

reg = <0xd1000000 0x1000>,
      <0xd10c0000 0x1000>,
      <0xd3000000 0x20000>,
     <0xd0c41000.0x1000>;
reg-names = "dbi", "atu", "config", "app";

[1] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller/dwc/pcie-intel-gw.c#L301
[2] https://lore.kernel.org/all/BY3PR19MB507667CE7531D863E1E5F8AEBDD82@BY3PR19MB5076.namprd19.prod.outlook.com/

Signed-off-by: Florian Eckert <fe@dev.tdt.de>
---
 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
index 54e2890ae6314ac6847fc23f49440d05d66d87d4..e4b781f57e8ae84a3ffc33635a421e1a5761587e 100644
--- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
@@ -29,12 +29,14 @@ properties:
   reg:
     items:
       - description: Controller control and status registers.
+      - description: Internal Address Translation Unit (iATU) registers.
       - description: PCIe configuration registers.
       - description: Controller application registers.
 
   reg-names:
     items:
       - const: dbi
+      - const: atu
       - const: config
       - const: app
 
@@ -94,9 +96,10 @@ examples:
       #address-cells = <3>;
       #size-cells = <2>;
       reg = <0xd0e00000 0x1000>,
+            <0xd0ec0000 0x1000>,
             <0xd2000000 0x800000>,
             <0xd0a41000 0x1000>;
-      reg-names = "dbi", "config", "app";
+      reg-names = "dbi", "atu", config", "app";
       linux,pci-domain = <0>;
       max-link-speed = <4>;
       bus-range = <0x00 0x08>;

-- 
2.47.3

[PATCH v2 7/7] MAINTAINERS: Remove bouncing intel-gw maintainer

[Florian Eckert]

The maintainer's email address has been bouncing for months. Mark the PCI
intel-gw driver as orphaned.

Signed-off-by: Florian Eckert <fe@dev.tdt.de>
---
 MAINTAINERS | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 96ea84948d76aff5e07579911d0f370ae13f481b..26f3b2e192fa9ef2e1c89d2310bebaa0a67dff00 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20505,9 +20505,8 @@ F:	Documentation/devicetree/bindings/pci/intel,keembay-pcie*
 F:	drivers/pci/controller/dwc/pcie-keembay.c
 
 PCIE DRIVER FOR INTEL LGM GW SOC
-M:	Chuanhua Lei <lchuanhua@maxlinear.com>
 L:	linux-pci@vger.kernel.org
-S:	Maintained
+S:	Orphan
 F:	Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
 F:	drivers/pci/controller/dwc/pcie-intel-gw.c
 

-- 
2.47.3

Re: [PATCH v2 6/7] dt-bindings: PCI: intel,lgm-pcie: Make atu resource mandatory

[Krzysztof Kozlowski]

On 30/03/2026 11:07, Florian Eckert wrote:
> The ATU information is already set in the dwc core if it is specified in
> the DTS. The driver uses its own value here [1]. This information is
> hardware specific and should therefore be maintained in the DTS rather
> than in the source.
> 
> Backwards compatibility is not an issue here [5], as the driver is
> exclusively used by Maxlinear.

What does that mean exactly? It is not used outside of Maxlinear
company, so it is purely internal device and no one outside of Maxlinear
has it?

Then we can as well remove it and I don't quite get why you are working
on this (since no one can use it outside of Maxlinear...).

> 
> Old DTS entry for PCIe:
> 
> reg = <0xd1000000 0x1000>,
>       <0xd3000000 0x20000>,
>       <0xd0c41000.0x1000>;
> reg-names = "dbi", "config", "app";
> 
> New DTS entry for PCIe:
> 
> reg = <0xd1000000 0x1000>,
>       <0xd10c0000 0x1000>,
>       <0xd3000000 0x20000>,
>      <0xd0c41000.0x1000>;
> reg-names = "dbi", "atu", "config", "app";

Drop, irrelevant. You still break all users of this binding.

Best regards,
Krzysztof

Re: [PATCH v2 6/7] dt-bindings: PCI: intel,lgm-pcie: Make atu resource mandatory

[Rob Herring (Arm)]

On Mon, 30 Mar 2026 11:07:16 +0200, Florian Eckert wrote:
> The ATU information is already set in the dwc core if it is specified in
> the DTS. The driver uses its own value here [1]. This information is
> hardware specific and should therefore be maintained in the DTS rather
> than in the source.
> 
> Backwards compatibility is not an issue here [5], as the driver is
> exclusively used by Maxlinear.
> 
> Old DTS entry for PCIe:
> 
> reg = <0xd1000000 0x1000>,
>       <0xd3000000 0x20000>,
>       <0xd0c41000.0x1000>;
> reg-names = "dbi", "config", "app";
> 
> New DTS entry for PCIe:
> 
> reg = <0xd1000000 0x1000>,
>       <0xd10c0000 0x1000>,
>       <0xd3000000 0x20000>,
>      <0xd0c41000.0x1000>;
> reg-names = "dbi", "atu", "config", "app";
> 
> [1] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller/dwc/pcie-intel-gw.c#L301
> [2] https://lore.kernel.org/all/BY3PR19MB507667CE7531D863E1E5F8AEBDD82@BY3PR19MB5076.namprd19.prod.outlook.com/
> 
> Signed-off-by: Florian Eckert <fe@dev.tdt.de>
> ---
>  Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Lexical error: Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dts:28.37-43 Unexpected 'config'
Error: Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dts:28.37-43 syntax error
FATAL ERROR: Unable to parse input tree
make[2]: *** [scripts/Makefile.dtbs:140: Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1601: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20260330-pcie-intel-gw-v2-6-8bd07367a298@dev.tdt.de

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v2 6/7] dt-bindings: PCI: intel,lgm-pcie: Make atu resource mandatory

[Florian Eckert]

On 2026-03-30 11:50, Krzysztof Kozlowski wrote:
> On 30/03/2026 11:07, Florian Eckert wrote:
>> The ATU information is already set in the dwc core if it is specified 
>> in
>> the DTS. The driver uses its own value here [1]. This information is
>> hardware specific and should therefore be maintained in the DTS rather
>> than in the source.
>> 
>> Backwards compatibility is not an issue here [5], as the driver is
>> exclusively used by Maxlinear.
> 
> What does that mean exactly? It is not used outside of Maxlinear
> company, so it is purely internal device and no one outside of 
> Maxlinear
> has it?

Background information:

The PCIe IP core is only available for Maxlinear’s URX851 and
URX850 SoCs. However, the chip was originally developed by Intel when
they acquired Lantiq’s home networking division in 2015 [1] for this
SoCs. In 2020 the home network division was sold to Maxlinear [2].

Since then, Maxlinear has been responsible for the driver. However,
their SDK is outdated and based on kernel 5.15. Other than that, not
much is happening! Even the developers listed as maintainers can no
longer be reached. When it came to the patch set, the email couldn't
be delivered  to the responsible developer
'Chuanhua Lei <lchuanhua@maxlinear.com>' either. The email bounced
back.

The company I work for is using the chip and is currently in the
process  of extracting the key components from the SDK so that the
SoC URX851/URX850 can work again with a mainline kernel again.

[1] 
https://www.intc.com/news-events/press-releases/detail/364/intel-to-acquire-lantiq-advancing-the-connected-home
[2] 
https://investors.maxlinear.com/press-releases/detail/395/maxlinear-to-acquire-intels-home-gateway-platform

> Then we can as well remove it and I don't quite get why you are working
> on this (since no one can use it outside of Maxlinear...).

Maxlinear continues to sell that SoC. They are *not' EOL.
It’s just that their Board Support Package (SDK) is no longer
up to date.

>> 
>> Old DTS entry for PCIe:
>> 
>> reg = <0xd1000000 0x1000>,
>>       <0xd3000000 0x20000>,
>>       <0xd0c41000.0x1000>;
>> reg-names = "dbi", "config", "app";
>> 
>> New DTS entry for PCIe:
>> 
>> reg = <0xd1000000 0x1000>,
>>       <0xd10c0000 0x1000>,
>>       <0xd3000000 0x20000>,
>>      <0xd0c41000.0x1000>;
>> reg-names = "dbi", "atu", "config", "app";
> 
> Drop, irrelevant. You still break all users of this binding.

As noted in link [3], a Maxlinear developer has stated that
backwards compatibility is not necessary here, as the IP core
is used exclusively by Maxlinear`s URX851 and URX850 SoC`s.

We use these SoCs in our Produkt for internet home gateway
routers.

[3] 
https://lore.kernel.org/all/BY3PR19MB507667CE7531D863E1E5F8AEBDD82@BY3PR19MB5076.namprd19.prod.outlook.com/

> Best regards,
> Krzysztof

Re: [PATCH v2 6/7] dt-bindings: PCI: intel,lgm-pcie: Make atu resource mandatory

[Krzysztof Kozlowski]

On Mon, Mar 30, 2026 at 12:52:16PM +0200, Florian Eckert wrote:
> 
> 
> On 2026-03-30 11:50, Krzysztof Kozlowski wrote:
> > On 30/03/2026 11:07, Florian Eckert wrote:
> > > The ATU information is already set in the dwc core if it is
> > > specified in
> > > the DTS. The driver uses its own value here [1]. This information is
> > > hardware specific and should therefore be maintained in the DTS rather
> > > than in the source.
> > > 
> > > Backwards compatibility is not an issue here [5], as the driver is
> > > exclusively used by Maxlinear.
> > 
> > What does that mean exactly? It is not used outside of Maxlinear
> > company, so it is purely internal device and no one outside of Maxlinear
> > has it?
> 
> Background information:
> 
> The PCIe IP core is only available for Maxlinear’s URX851 and
> URX850 SoCs. However, the chip was originally developed by Intel when
> they acquired Lantiq’s home networking division in 2015 [1] for this
> SoCs. In 2020 the home network division was sold to Maxlinear [2].
> 
> Since then, Maxlinear has been responsible for the driver. However,
> their SDK is outdated and based on kernel 5.15. Other than that, not

v5.15 DTS user of this binding is still valid user. Why would you break
it?

> much is happening! Even the developers listed as maintainers can no
> longer be reached. When it came to the patch set, the email couldn't
> be delivered  to the responsible developer
> 'Chuanhua Lei <lchuanhua@maxlinear.com>' either. The email bounced
> back.

Not really relevant to my question. I understand that this is not
maintained, but I asked about backwards compatibility.

Backwards compatibility of the ABI means that existing in-tree and ALL
out-of-tree users of given ABI must keep working fine. Properties with
lists have strictly defined order, so changing that order is considered
ABI break, unless you prove otherwise.

Calling code unmantained is not proving that ABI is not broken.

> 
> The company I work for is using the chip and is currently in the
> process  of extracting the key components from the SDK so that the
> SoC URX851/URX850 can work again with a mainline kernel again.
> 
> [1] https://www.intc.com/news-events/press-releases/detail/364/intel-to-acquire-lantiq-advancing-the-connected-home
> [2] https://investors.maxlinear.com/press-releases/detail/395/maxlinear-to-acquire-intels-home-gateway-platform
> 
> > Then we can as well remove it and I don't quite get why you are working
> > on this (since no one can use it outside of Maxlinear...).
> 
> Maxlinear continues to sell that SoC. They are *not' EOL.
> It’s just that their Board Support Package (SDK) is no longer
> up to date.
> 
> > > 
> > > Old DTS entry for PCIe:
> > > 
> > > reg = <0xd1000000 0x1000>,
> > >       <0xd3000000 0x20000>,
> > >       <0xd0c41000.0x1000>;
> > > reg-names = "dbi", "config", "app";
> > > 
> > > New DTS entry for PCIe:
> > > 
> > > reg = <0xd1000000 0x1000>,
> > >       <0xd10c0000 0x1000>,
> > >       <0xd3000000 0x20000>,
> > >      <0xd0c41000.0x1000>;
> > > reg-names = "dbi", "atu", "config", "app";
> > 
> > Drop, irrelevant. You still break all users of this binding.
> 
> As noted in link [3], a Maxlinear developer has stated that
> backwards compatibility is not necessary here, as the IP core
> is used exclusively by Maxlinear`s URX851 and URX850 SoC`s.
> 
> We use these SoCs in our Produkt for internet home gateway
> routers.
> 
> [3] https://lore.kernel.org/all/BY3PR19MB507667CE7531D863E1E5F8AEBDD82@BY3PR19MB5076.namprd19.prod.outlook.com/

OK, yet I do not understand "driver is only used for internally". How
Maxlinear engineer can know all projects around the world and all 7
billion people if they use that ABI? And if they are right and no one
uses it outside of Maxlinear, then let's drop this code. It's dead code,
no?

Best regards,
Krzysztof

Re: [PATCH v2 6/7] dt-bindings: PCI: intel,lgm-pcie: Make atu resource mandatory

[Rob Herring]

On Mon, Mar 30, 2026 at 11:07:16AM +0200, Florian Eckert wrote:
> The ATU information is already set in the dwc core if it is specified in
> the DTS. The driver uses its own value here [1]. This information is
> hardware specific and should therefore be maintained in the DTS rather
> than in the source.
> 
> Backwards compatibility is not an issue here [5], as the driver is
> exclusively used by Maxlinear.
> 
> Old DTS entry for PCIe:
> 
> reg = <0xd1000000 0x1000>,
>       <0xd3000000 0x20000>,
>       <0xd0c41000.0x1000>;
> reg-names = "dbi", "config", "app";
> 
> New DTS entry for PCIe:
> 
> reg = <0xd1000000 0x1000>,
>       <0xd10c0000 0x1000>,
>       <0xd3000000 0x20000>,
>      <0xd0c41000.0x1000>;
> reg-names = "dbi", "atu", "config", "app";
> 
> [1] https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller/dwc/pcie-intel-gw.c#L301
> [2] https://lore.kernel.org/all/BY3PR19MB507667CE7531D863E1E5F8AEBDD82@BY3PR19MB5076.namprd19.prod.outlook.com/
> 
> Signed-off-by: Florian Eckert <fe@dev.tdt.de>
> ---
>  Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
> index 54e2890ae6314ac6847fc23f49440d05d66d87d4..e4b781f57e8ae84a3ffc33635a421e1a5761587e 100644
> --- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
> @@ -29,12 +29,14 @@ properties:
>    reg:
>      items:
>        - description: Controller control and status registers.
> +      - description: Internal Address Translation Unit (iATU) registers.
>        - description: PCIe configuration registers.
>        - description: Controller application registers.
>  
>    reg-names:
>      items:
>        - const: dbi
> +      - const: atu

Put this at the end and add 'minItems: 3' and you avoid any ABI issues.

>        - const: config
>        - const: app
>  

Re: [PATCH v2 4/7] PCI: intel-gw: Add start_link callback function

[kernel test robot]

Hi Florian,

kernel test robot noticed the following build warnings:

[auto build test WARNING on f338e77383789c0cae23ca3d48adcc5e9e137e3c]

url:    https://github.com/intel-lab-lkp/linux/commits/Florian-Eckert/PCI-intel-gw-Remove-unused-define/20260401-051352
base:   f338e77383789c0cae23ca3d48adcc5e9e137e3c
patch link:    https://lore.kernel.org/r/20260330-pcie-intel-gw-v2-4-8bd07367a298%40dev.tdt.de
patch subject: [PATCH v2 4/7] PCI: intel-gw: Add start_link callback function
config: sparc-randconfig-002-20260401 (https://download.01.org/0day-ci/archive/20260401/202604011153.Qo18yHpp-lkp@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260401/202604011153.Qo18yHpp-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202604011153.Qo18yHpp-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/pci/controller/dwc/pcie-intel-gw.c: In function 'intel_pcie_host_setup':
>> drivers/pci/controller/dwc/pcie-intel-gw.c:329:1: warning: label 'err' defined but not used [-Wunused-label]
    err:
    ^~~


vim +/err +329 drivers/pci/controller/dwc/pcie-intel-gw.c

6cbd614d1f7c81 Florian Eckert 2026-03-30  296  
733770d4a2bea0 Fan Fei        2021-12-22  297  static int intel_pcie_host_setup(struct intel_pcie *pcie)
ed22aaaede44f6 Dilip Kota     2019-12-09  298  {
ed22aaaede44f6 Dilip Kota     2019-12-09  299  	int ret;
733770d4a2bea0 Fan Fei        2021-12-22  300  	struct dw_pcie *pci = &pcie->pci;
ed22aaaede44f6 Dilip Kota     2019-12-09  301  
733770d4a2bea0 Fan Fei        2021-12-22  302  	intel_pcie_core_rst_assert(pcie);
733770d4a2bea0 Fan Fei        2021-12-22  303  	intel_pcie_device_rst_assert(pcie);
733770d4a2bea0 Fan Fei        2021-12-22  304  	intel_pcie_core_rst_deassert(pcie);
ed22aaaede44f6 Dilip Kota     2019-12-09  305  
1927e1ec66a6ee Florian Eckert 2026-03-30  306  	/* Controller clock must be provided earlier than PHY */
733770d4a2bea0 Fan Fei        2021-12-22  307  	ret = clk_prepare_enable(pcie->core_clk);
ed22aaaede44f6 Dilip Kota     2019-12-09  308  	if (ret) {
733770d4a2bea0 Fan Fei        2021-12-22  309  		dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret);
ed22aaaede44f6 Dilip Kota     2019-12-09  310  		goto clk_err;
ed22aaaede44f6 Dilip Kota     2019-12-09  311  	}
ed22aaaede44f6 Dilip Kota     2019-12-09  312  
1cc9a559993a4a Rob Herring    2020-11-05  313  	pci->atu_base = pci->dbi_base + 0xC0000;
1cc9a559993a4a Rob Herring    2020-11-05  314  
1927e1ec66a6ee Florian Eckert 2026-03-30  315  	ret = phy_init(pcie->phy);
1927e1ec66a6ee Florian Eckert 2026-03-30  316  	if (ret)
1927e1ec66a6ee Florian Eckert 2026-03-30  317  		goto phy_err;
1927e1ec66a6ee Florian Eckert 2026-03-30  318  
733770d4a2bea0 Fan Fei        2021-12-22  319  	intel_pcie_ltssm_disable(pcie);
733770d4a2bea0 Fan Fei        2021-12-22  320  	intel_pcie_link_setup(pcie);
1cc9a559993a4a Rob Herring    2020-11-05  321  	intel_pcie_init_n_fts(pci);
ce06bf570390fb Serge Semin    2022-06-24  322  
1cc9a559993a4a Rob Herring    2020-11-05  323  	dw_pcie_upconfig_setup(pci);
1cc9a559993a4a Rob Herring    2020-11-05  324  
4db57fd92a7d2d Florian Eckert 2026-03-30  325  	intel_pcie_core_irq_enable(pcie);
ed22aaaede44f6 Dilip Kota     2019-12-09  326  
ed22aaaede44f6 Dilip Kota     2019-12-09  327  	return 0;
ed22aaaede44f6 Dilip Kota     2019-12-09  328  
1927e1ec66a6ee Florian Eckert 2026-03-30 @329  err:
1927e1ec66a6ee Florian Eckert 2026-03-30  330  	phy_exit(pcie->phy);
1927e1ec66a6ee Florian Eckert 2026-03-30  331  phy_err:
733770d4a2bea0 Fan Fei        2021-12-22  332  	clk_disable_unprepare(pcie->core_clk);
ed22aaaede44f6 Dilip Kota     2019-12-09  333  clk_err:
733770d4a2bea0 Fan Fei        2021-12-22  334  	intel_pcie_core_rst_assert(pcie);
ed22aaaede44f6 Dilip Kota     2019-12-09  335  
ed22aaaede44f6 Dilip Kota     2019-12-09  336  	return ret;
ed22aaaede44f6 Dilip Kota     2019-12-09  337  }
ed22aaaede44f6 Dilip Kota     2019-12-09  338  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v2 4/7] PCI: intel-gw: Add start_link callback function

[kernel test robot]

Hi Florian,

kernel test robot noticed the following build warnings:

[auto build test WARNING on f338e77383789c0cae23ca3d48adcc5e9e137e3c]

url:    https://github.com/intel-lab-lkp/linux/commits/Florian-Eckert/PCI-intel-gw-Remove-unused-define/20260401-051352
base:   f338e77383789c0cae23ca3d48adcc5e9e137e3c
patch link:    https://lore.kernel.org/r/20260330-pcie-intel-gw-v2-4-8bd07367a298%40dev.tdt.de
patch subject: [PATCH v2 4/7] PCI: intel-gw: Add start_link callback function
config: arm64-randconfig-001-20260401 (https://download.01.org/0day-ci/archive/20260401/202604011157.4RiSNWVi-lkp@intel.com/config)
compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260401/202604011157.4RiSNWVi-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202604011157.4RiSNWVi-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pci/controller/dwc/pcie-intel-gw.c:329:1: warning: unused label 'err' [-Wunused-label]
     329 | err:
         | ^~~~
   1 warning generated.


vim +/err +329 drivers/pci/controller/dwc/pcie-intel-gw.c

6cbd614d1f7c81 Florian Eckert 2026-03-30  296  
733770d4a2bea0 Fan Fei        2021-12-22  297  static int intel_pcie_host_setup(struct intel_pcie *pcie)
ed22aaaede44f6 Dilip Kota     2019-12-09  298  {
ed22aaaede44f6 Dilip Kota     2019-12-09  299  	int ret;
733770d4a2bea0 Fan Fei        2021-12-22  300  	struct dw_pcie *pci = &pcie->pci;
ed22aaaede44f6 Dilip Kota     2019-12-09  301  
733770d4a2bea0 Fan Fei        2021-12-22  302  	intel_pcie_core_rst_assert(pcie);
733770d4a2bea0 Fan Fei        2021-12-22  303  	intel_pcie_device_rst_assert(pcie);
733770d4a2bea0 Fan Fei        2021-12-22  304  	intel_pcie_core_rst_deassert(pcie);
ed22aaaede44f6 Dilip Kota     2019-12-09  305  
1927e1ec66a6ee Florian Eckert 2026-03-30  306  	/* Controller clock must be provided earlier than PHY */
733770d4a2bea0 Fan Fei        2021-12-22  307  	ret = clk_prepare_enable(pcie->core_clk);
ed22aaaede44f6 Dilip Kota     2019-12-09  308  	if (ret) {
733770d4a2bea0 Fan Fei        2021-12-22  309  		dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret);
ed22aaaede44f6 Dilip Kota     2019-12-09  310  		goto clk_err;
ed22aaaede44f6 Dilip Kota     2019-12-09  311  	}
ed22aaaede44f6 Dilip Kota     2019-12-09  312  
1cc9a559993a4a Rob Herring    2020-11-05  313  	pci->atu_base = pci->dbi_base + 0xC0000;
1cc9a559993a4a Rob Herring    2020-11-05  314  
1927e1ec66a6ee Florian Eckert 2026-03-30  315  	ret = phy_init(pcie->phy);
1927e1ec66a6ee Florian Eckert 2026-03-30  316  	if (ret)
1927e1ec66a6ee Florian Eckert 2026-03-30  317  		goto phy_err;
1927e1ec66a6ee Florian Eckert 2026-03-30  318  
733770d4a2bea0 Fan Fei        2021-12-22  319  	intel_pcie_ltssm_disable(pcie);
733770d4a2bea0 Fan Fei        2021-12-22  320  	intel_pcie_link_setup(pcie);
1cc9a559993a4a Rob Herring    2020-11-05  321  	intel_pcie_init_n_fts(pci);
ce06bf570390fb Serge Semin    2022-06-24  322  
1cc9a559993a4a Rob Herring    2020-11-05  323  	dw_pcie_upconfig_setup(pci);
1cc9a559993a4a Rob Herring    2020-11-05  324  
4db57fd92a7d2d Florian Eckert 2026-03-30  325  	intel_pcie_core_irq_enable(pcie);
ed22aaaede44f6 Dilip Kota     2019-12-09  326  
ed22aaaede44f6 Dilip Kota     2019-12-09  327  	return 0;
ed22aaaede44f6 Dilip Kota     2019-12-09  328  
1927e1ec66a6ee Florian Eckert 2026-03-30 @329  err:
1927e1ec66a6ee Florian Eckert 2026-03-30  330  	phy_exit(pcie->phy);
1927e1ec66a6ee Florian Eckert 2026-03-30  331  phy_err:
733770d4a2bea0 Fan Fei        2021-12-22  332  	clk_disable_unprepare(pcie->core_clk);
ed22aaaede44f6 Dilip Kota     2019-12-09  333  clk_err:
733770d4a2bea0 Fan Fei        2021-12-22  334  	intel_pcie_core_rst_assert(pcie);
ed22aaaede44f6 Dilip Kota     2019-12-09  335  
ed22aaaede44f6 Dilip Kota     2019-12-09  336  	return ret;
ed22aaaede44f6 Dilip Kota     2019-12-09  337  }
ed22aaaede44f6 Dilip Kota     2019-12-09  338  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v2 6/7] dt-bindings: PCI: intel,lgm-pcie: Make atu resource mandatory

[Florian Eckert]

On 2026-03-31 17:21, Rob Herring wrote:
> On Mon, Mar 30, 2026 at 11:07:16AM +0200, Florian Eckert wrote:
>> The ATU information is already set in the dwc core if it is specified 
>> in
>> the DTS. The driver uses its own value here [1]. This information is
>> hardware specific and should therefore be maintained in the DTS rather
>> than in the source.
>> 
>> Backwards compatibility is not an issue here [5], as the driver is
>> exclusively used by Maxlinear.
>> 
>> Old DTS entry for PCIe:
>> 
>> reg = <0xd1000000 0x1000>,
>>       <0xd3000000 0x20000>,
>>       <0xd0c41000.0x1000>;
>> reg-names = "dbi", "config", "app";
>> 
>> New DTS entry for PCIe:
>> 
>> reg = <0xd1000000 0x1000>,
>>       <0xd10c0000 0x1000>,
>>       <0xd3000000 0x20000>,
>>      <0xd0c41000.0x1000>;
>> reg-names = "dbi", "atu", "config", "app";
>> 
>> [1] 
>> https://elixir.bootlin.com/linux/v6.19.10/source/drivers/pci/controller/dwc/pcie-intel-gw.c#L301
>> [2] 
>> https://lore.kernel.org/all/BY3PR19MB507667CE7531D863E1E5F8AEBDD82@BY3PR19MB5076.namprd19.prod.outlook.com/
>> 
>> Signed-off-by: Florian Eckert <fe@dev.tdt.de>
>> ---
>>  Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | 5 ++++-
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml 
>> b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
>> index 
>> 54e2890ae6314ac6847fc23f49440d05d66d87d4..e4b781f57e8ae84a3ffc33635a421e1a5761587e 
>> 100644
>> --- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
>> @@ -29,12 +29,14 @@ properties:
>>    reg:
>>      items:
>>        - description: Controller control and status registers.
>> +      - description: Internal Address Translation Unit (iATU) 
>> registers.
>>        - description: PCIe configuration registers.
>>        - description: Controller application registers.
>> 
>>    reg-names:
>>      items:
>>        - const: dbi
>> +      - const: atu
> 
> Put this at the end and add 'minItems: 3' and you avoid any ABI issues.

Unfortunately, I misunderstood what you meant. This is still wrong in v3 
[1]
I send to day. I’ve only changed it in the documentation. I forgot to do
that in the example, as I didn’t realize that we can not always access
resources by name, but also by index. That’s why the order matters. I’ve 
got
it now.

Thanks!

My mistake – I’ll change that in v4 tomorrow so that your bot is happy 
too.

--
Florian

[1] 
https://lore.kernel.org/all/20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de/T/#t

> 
>>        - const: config
>>        - const: app
>>