From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ACE1408223; Tue, 31 Mar 2026 15:26:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774970788; cv=none; b=siiNkG0mggWZRvpgiLljGAl6DQCLeXdOu/IH245bOQbSfKTTnXgGlZtHhIBUo8GRbNEjsUFphqHpylfYvqJZy5tSy87WNVfoXqe+HihcgLqTnyL5SKMvr/med4DWQH9e+PbT1e5lnICmIzI8StLf8/F/28sSSz3Bv9TtTa6Ipxo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774970788; c=relaxed/simple; bh=pmmaAhvStRBkp4oWLcAqxqNFdL9vS/g5gYPrhXfeSGI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mu6MDt+vuYSLtwSkM89IMnN7h7LqmT86M3m7wQZG5ukNZG0V3r4h51svCWicD9dvRx8ZQ0c1gkKoF79GQtwbr+/V6Gi9fxsT0pEX2WUw54j7/cdA8eQp/HdRP2ozurA/yenCU2DY7B/rNChEBDV34r15KuSZ2Oo2e9hXMeQ8Ty0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=HOKPIgE1; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="HOKPIgE1" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 16EDD4E4288B; Tue, 31 Mar 2026 15:26:26 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id E0C4F6029D; Tue, 31 Mar 2026 15:26:25 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9157F10450296; Tue, 31 Mar 2026 17:26:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1774970785; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=B6t/jwdDx9/bs2Up2VlLVQz3B+xYRrW/vD22H3nG9tg=; b=HOKPIgE1gjKgdkrW6flMzzZ6YQQoFvVRHonOZS82T1aK5gg8yLDkruQQMLdl0CK+C4BgGW Ml0wlkvFRYx9Vjp5kLGYb+cwpJMt09+2SuDRwo9Z5+VBO1Z5OnxH0OtMGGzwH87aCXT98M IccBAABZP0EIKCBvJDpZoNLn4/5C4NqA51d5v5aYyyDGoDRO3SMBZ16fWtiYqcIb9CWYTl tBSo2genuM/RC7YdgyeBhg5y3M8Noz9UafgtOy389yvTNC4Ul3dhWBUpeW0OMBsDPvWsfY 8/4k83jVkWNR7lWVHCnxOzf4YyhJWLs7X65XV+KPR/7xTyT0UxFE5009PtGGsg== From: "Herve Codina (Schneider Electric)" To: Wolfram Sang , Herve Codina , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: [PATCH 1/4] dt-bindings: timer: Add the Renesas RZ/N1 timer Date: Tue, 31 Mar 2026 17:26:12 +0200 Message-ID: <20260331152616.197031-2-herve.codina@bootlin.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260331152616.197031-1-herve.codina@bootlin.com> References: <20260331152616.197031-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 The Renesas RZ/N1 timer block controller is the controller in charge of timers available in the Renesas RZ/N1 SoCs family. This controller handles 8 timers: - 6 16-bit timers - 2 32-bit timers Signed-off-by: Herve Codina (Schneider Electric) --- .../bindings/timer/renesas,rzn1-timer.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml b/Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml new file mode 100644 index 000000000000..b9a725837d7c --- /dev/null +++ b/Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/renesas,rzn1-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 timers + +maintainers: + - Herve Codina + +description: | + The Renesas RZ/N1 SoCs timers block controller is composed of 8 independent + timers. + - 6 are 16-bit timers + - 2 are 32-bit timers + + Each timer has its own interrupt line and can work in either one-shot or + periodic mode. + +properties: + compatible: + items: + - const: renesas,r9a06g032-timer # RZ/N1D + - const: renesas,rzn1-timer + + reg: + maxItems: 1 + + clocks: + items: + - description: APB internal bus clock + + clock-names: + items: + - const: pclk + + power-domains: + maxItems: 1 + + interrupts: + minItems: 8 + maxItems: 8 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + timer@51001000 { + compatible = "renesas,r9a06g032-timer", "renesas,rzn1-timer"; + reg = <0x51001000 0x400>; + clocks = <&sysctrl R9A06G032_HCLK_TIMER0>; + clock-names = "pclk"; + power-domains = <&sysctrl>; + interrupts = , + , + , + , + , + , + , + ; + }; +... -- 2.53.0