From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC6F531D366; Tue, 31 Mar 2026 17:13:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774977187; cv=none; b=RsNcuZ6J/WVDNe+kZtCbF9P2PIOHPtYXn8poq/V//3gyDQvCHQf0gVJh3dhLrVYLck6A+KRw4b0+b9pGU+0Kq+aHSY9Qmi/aHxpHPoIYh0cWmroStOFIPBi/0GND1DS2hAxJnFOT6hssaaRTeGkm2Bc9zwsjzh7+oxWS/DH7clo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774977187; c=relaxed/simple; bh=86GbQFzTZ0huTRYyz379S7ayUIzfenjwN7Y5u7weLuI=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=ksS7Ht1MIjWuWpODa2PdeWgSWDkNXz/K2gFAPesXhgMfEW3qQMfhIpK55m01XrdRFpf5Ag9KwHrvVNi7H/E9SJPaJfu9Uecdzj0MAENUHWCAqUfflg/cCoHUmUwjjHLZ5q/QXJjxBkOrzVlx36j03i3UFNPYE8yWocv44T3U1+Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [223.166.95.230]) by APP-03 (Coremail) with SMTP id rQCowABnhdyRAMxpydRzDA--.42156S2; Wed, 01 Apr 2026 01:12:50 +0800 (CST) From: Han Gao To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Han Gao , Zixian Zeng Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Han Gao Subject: [PATCH 0/2] riscv: sophgo: sg2042: Enable PCIe DMA coherence Date: Wed, 1 Apr 2026 01:12:46 +0800 Message-ID: <20260331171248.973014-1-gaohan@iscas.ac.cn> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:rQCowABnhdyRAMxpydRzDA--.42156S2 X-Coremail-Antispam: 1UD129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73 VFW2AGmfu7bjvjm3AaLaJ3UjIYCTnIWjp_UUUYm7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E 6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28Cjx kF64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8I cVCY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26F4j6r4UJwA2z4x0Y4vEx4A2js IEc7CjxVAFwI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAK zVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx 8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIF xwACI402YVCY1x02628vn2kIc2xKxwCF04k20xvY0x0EwIxGrwCF54CYxVCY1x0262kKe7 AKxVW8ZVWrXwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I 3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIx AIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAI cVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2js IEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUQvtAUUUUU= X-CM-SenderInfo: xjdrxt3q6l2u1dvotugofq/1tbiBg0DDGnL4ih7xAAAsT The SG2042 hardware design supports cache-coherent PCIe. With recent firmware updates [1], it allows to use DMA coherent. [1] https://github.com/sophgo/edk2-non-osi/commit/017a5aea26a066fd2bf501b7893937183165af36 Han Gao (2): dt-bindings: pci: sophgo: Add dma-coherent property for SG2042 riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers .../devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml | 3 +++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++ 2 files changed, 7 insertions(+) -- 2.47.3