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Wed, 01 Apr 2026 01:16:46 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Wed, 1 Apr 2026 01:16:45 -0700 Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Wed, 1 Apr 2026 01:16:44 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Wed, 1 Apr 2026 01:16:43 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 529973F7055; Wed, 1 Apr 2026 01:16:41 -0700 (PDT) From: Geetha sowjanya To: , , , CC: , , Subject: [PATCH v3 0/2] perf: marvell: Add CN20K DDR PMU support Date: Wed, 1 Apr 2026 13:46:38 +0530 Message-ID: <20260401081640.23740-1-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: yIu8xWzqBm4JafdGAdkZHYflZP05CU_2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAxMDA3MyBTYWx0ZWRfXxNu3LdOuiBmW tP6zsk4IFwRxoy7zl3AR/ATh4ajGp6yYsUiKltl645+cjnFOY97bgfvvtgmG1fAYoXRREWVf4CV 6SFzQILM9rb4b8MI8o/KrgNJL2SXgBWsQyiT3tJJNAEkKFfeCJ2RLvQFEGPiu0IVLR0U0k6YoS3 Z5FW2usPswuxk52RCtbQ8poLzI16GZSMMDYS31UoCU6pQGW+wfriFMhVL0HKDpnFzzn9ZUoKt1X /bG23gqp5kz/VmVzPDPjPA5TI1c/tNktRjxdIR8XfU9rBiVTv/MrQXmLYbJvuiGa1QEC+tU5WCK igzFg4OdIbQBF0H51WmcZVbS3956mmlNaIGLPikH4QaLRC1ZZYj4xJ9IYxXg8v2JpzeAQEAtjna hTLjkJxXxltdAynCEO9nWUdTc+Yjn+nj7FvZXnxU4fOK5+XZkaKwhvLX+G142dMoftpkwoRwzVu YM0O5LY7CTUy4OJUQ5w== X-Proofpoint-ORIG-GUID: yIu8xWzqBm4JafdGAdkZHYflZP05CU_2 X-Authority-Analysis: v=2.4 cv=EKMLElZC c=1 sm=1 tr=0 ts=69ccd46e cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=g9OxYFsRBXyit7-cW8EA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-01_02,2026-04-01_01,2025-10-01_01 This series adds support for the Marvell CN20K DRAM Subsystem (DSS) performance monitor in the existing marvell_cn10k_ddr_pmu driver, and documents the device tree binding for the new compatible string. The CN20K PMU provides eight programmable counters and two fixed counters (DDR reads and writes). Patch 1 adds the devicetree schema for "marvell,cn20k-ddr-pmu". Patch 2 wires OF and ACPI (MRVL000B) match entries, adds CN20K register offsets and event maps, and refactors platform data to use silicon variant flags. Signed-off-by: Geetha sowjanya Changes in v2: - Fixed YAML syntax error triggered by a tab character in the examples section, which caused dt_binding_check to fail. Changes in v1: - Added a description field to the binding. - Simplified the compatible property using 'const' instead of 'items/enum'. - Updated the example node name to include a unit-address matching the reg base. Geetha sowjanya (2): dt-bindings: perf: marvell: Document CN20K DDR PMU perf: marvell: Add CN20K DDR PMU support .../bindings/perf/marvell-cn20k-ddr.yaml | 37 ++++ drivers/perf/marvell_cn10k_ddr_pmu.c | 186 ++++++++++++++++-- 2 files changed, 207 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml -- 2.25.1