From: Conor Dooley <conor@kernel.org>
To: Changhuang Liang <changhuang.liang@starfivetech.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>,
Kees Cook <kees@kernel.org>,
"Gustavo A . R . Silva" <gustavoars@kernel.org>,
Richard Cochran <richardcochran@gmail.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-hardening@vger.kernel.org, netdev@vger.kernel.org,
Sia Jee Heng <jeeheng.sia@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>
Subject: Re: [PATCH v1 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes
Date: Thu, 2 Apr 2026 13:14:44 +0100 [thread overview]
Message-ID: <20260402-fox-overhand-9a45ec670bce@spud> (raw)
In-Reply-To: <20260402105523.447523-23-changhuang.liang@starfivetech.com>
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On Thu, Apr 02, 2026 at 03:55:23AM -0700, Changhuang Liang wrote:
> Add clocks and resets nodes for JHB100 RISC-V BMC SoC. They contain
> sys0crg/sys1crg/sys2crg/per0crg/per1crg/per2crg/per3crg.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jhb100.dtsi | 198 ++++++++++++++++++++++-
> 1 file changed, 195 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> index 4d03470f78ab..700d00f800bc 100644
> --- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> @@ -4,6 +4,8 @@
> */
>
> /dts-v1/;
> +#include <dt-bindings/clock/starfive,jhb100-crg.h>
> +#include <dt-bindings/reset/starfive,jhb100-crg.h>
>
> / {
> compatible = "starfive,jhb100";
> @@ -268,12 +270,96 @@ pmu {
> <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */
> };
>
> - clk_uart: clk-uart {
> - compatible = "fixed-clock"; /* Initial clock handler for UART */
> + osc: osc {
> + compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <25000000>;
> };
Is this really on the SoC?
>
> + pll0: pll0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <2400000000>;
> + };
What's providing all of these PLLs? Are they all fixed-frequency on-chip
PLLs without an off-chip reference? I find that somewhat unlikely.
Since devicetrees are now being imported into U-Boot, it's important to
make sure that I'm not merging fixed-clocks that later get replaced by
dedicated drivers that U-Boot won't have.
To that end, I won't apply the series this depends on without this patch
being applied at the same time.
> +
> + pll1: pll1 {
Also, none of these follow the preferred naming scheme for
fixed-frequency clocks. Go look at the binding for how they should be,
if they are too be kept.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1000000000>;
> + };
Cheers,
Conor.
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next prev parent reply other threads:[~2026-04-02 12:14 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-02 10:55 [PATCH v1 00/22] Add basic clocks and resets for JHB100 SoC Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 01/22] reset: starfive: Rename file name "jh71x0" to "common" Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 02/22] reset: starfive: Convert the word "jh71x0" to "starfive" Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 03/22] clk: starfive: Rename file name "jh71x0" to "common" Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 04/22] clk: starfive: Convert the word "jh71x0" to "starfive" Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 05/22] dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator Changhuang Liang
2026-04-02 12:22 ` Philipp Zabel
2026-04-03 0:53 ` Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 06/22] clk: starfive: Add JHB100 System-0 clock generator driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 07/22] dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 08/22] clk: starfive: Add JHB100 System-1 clock generator driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 09/22] dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 10/22] clk: starfive: Add JHB100 System-2 clock generator driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 11/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 12/22] clk: starfive: Introduce inverter and divider Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 13/22] clk: starfive: Expand the storage of clock parent index Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 14/22] clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 15/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 16/22] clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 17/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator Changhuang Liang
2026-04-04 11:34 ` Krzysztof Kozlowski
2026-04-02 10:55 ` [PATCH v1 18/22] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 19/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 20/22] clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 21/22] reset: starfive: Add StarFive JHB100 reset driver Changhuang Liang
2026-04-02 12:23 ` Philipp Zabel
2026-04-02 10:55 ` [PATCH v1 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes Changhuang Liang
2026-04-02 12:14 ` Conor Dooley [this message]
2026-04-03 1:07 ` Changhuang Liang
2026-04-03 14:03 ` Conor Dooley
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