From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 541DC3DCDA6; Thu, 2 Apr 2026 12:14:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775132092; cv=none; b=WMf6sRHJEOLH+Z3OpEm3+6Uku4gmgNHjrD5hfS3UYEfn/nKjBsw2usMXsge4aSzyu1XNzJ+Asc/0xddu+m1y09YxCNk96PB2iyUUWC84eVSEbSIRebGCs5Q82sqPX3HePJcDaDkM718i07b+qgbTS16GpJ07VIHdL49kwgfwwb0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775132092; c=relaxed/simple; bh=EqYl1q6OHzj9GF2+s+7JBq9ShRG/TNsV61jcIPYVR9U=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=UZlo2Z4CFJ9EP3rfiFTBiEQ5+Lya3qMMD5Eh2OTDPGsAbFi5WfZivw89FGH5fMvFXiV7PtcPX7hxdjtI4QLqsQZhtfjcFGy1eZFeX8YpUz3p200oXCvInoL+sy9TMN9sLyvsn9Zzw64M4MYmhwsTlaEL6YIWH8KzAasgR30RdKk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oqIp9oK/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oqIp9oK/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 59337C19423; Thu, 2 Apr 2026 12:14:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775132091; bh=EqYl1q6OHzj9GF2+s+7JBq9ShRG/TNsV61jcIPYVR9U=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=oqIp9oK/CmPGFtTrYHBXVTt3YRR7hvL/Lj8X/qA4v6UR4032SX75xrawsWktC3F/k DqXrln9xWd7/rAYk5YlSaKL2NorONWEC7QstrmLMww5lHQv+fYRj3rw39v7b2uk+e4 hZ/8+zV6pf/uLAXgGLuW5mJg5Oz2wRmYs/UUPF+oy/TETpwV0KVuo1s9+dj9fiQ9Ed YiojNiERmlBXh/fSNwIqZpk5tnX5IUGwLeIFo4P+8wtPr09MIGImnfaWcEmEbPj++/ +ftgRIUYnchCsI2dhmx3SiJ4kcLBqa/DyTzBJpSAxvDX44c38LX0eexi21Fs/Wuu0+ GQrx7liM/DJ8w== Date: Thu, 2 Apr 2026 13:14:44 +0100 From: Conor Dooley To: Changhuang Liang Cc: Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Philipp Zabel , Emil Renner Berthing , Kees Cook , "Gustavo A . R . Silva" , Richard Cochran , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-hardening@vger.kernel.org, netdev@vger.kernel.org, Sia Jee Heng , Hal Feng , Ley Foon Tan Subject: Re: [PATCH v1 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes Message-ID: <20260402-fox-overhand-9a45ec670bce@spud> References: <20260402105523.447523-1-changhuang.liang@starfivetech.com> <20260402105523.447523-23-changhuang.liang@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="i9/X0Hs31jPOYl+N" Content-Disposition: inline In-Reply-To: <20260402105523.447523-23-changhuang.liang@starfivetech.com> --i9/X0Hs31jPOYl+N Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Apr 02, 2026 at 03:55:23AM -0700, Changhuang Liang wrote: > Add clocks and resets nodes for JHB100 RISC-V BMC SoC. They contain > sys0crg/sys1crg/sys2crg/per0crg/per1crg/per2crg/per3crg. >=20 > Signed-off-by: Changhuang Liang > --- > arch/riscv/boot/dts/starfive/jhb100.dtsi | 198 ++++++++++++++++++++++- > 1 file changed, 195 insertions(+), 3 deletions(-) >=20 > diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/d= ts/starfive/jhb100.dtsi > index 4d03470f78ab..700d00f800bc 100644 > --- a/arch/riscv/boot/dts/starfive/jhb100.dtsi > +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi > @@ -4,6 +4,8 @@ > */ > =20 > /dts-v1/; > +#include > +#include > =20 > / { > compatible =3D "starfive,jhb100"; > @@ -268,12 +270,96 @@ pmu { > <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */ > }; > =20 > - clk_uart: clk-uart { > - compatible =3D "fixed-clock"; /* Initial clock handler for UART */ > + osc: osc { > + compatible =3D "fixed-clock"; > #clock-cells =3D <0>; > clock-frequency =3D <25000000>; > }; Is this really on the SoC? > =20 > + pll0: pll0 { > + compatible =3D "fixed-clock"; > + #clock-cells =3D <0>; > + clock-frequency =3D <2400000000>; > + }; What's providing all of these PLLs? Are they all fixed-frequency on-chip PLLs without an off-chip reference? I find that somewhat unlikely. Since devicetrees are now being imported into U-Boot, it's important to make sure that I'm not merging fixed-clocks that later get replaced by dedicated drivers that U-Boot won't have. To that end, I won't apply the series this depends on without this patch being applied at the same time. > + > + pll1: pll1 { Also, none of these follow the preferred naming scheme for fixed-frequency clocks. Go look at the binding for how they should be, if they are too be kept. > + compatible =3D "fixed-clock"; > + #clock-cells =3D <0>; > + clock-frequency =3D <1000000000>; > + }; Cheers, Conor. --i9/X0Hs31jPOYl+N Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCac5dtAAKCRB4tDGHoIJi 0uQHAP0WzBeqVfuYIxoQ5RQ7zJEaN6Xi9MLvyjrUg80WfHDtYwEAlx6dQ13WnFUI p3u5nsP2s7rO8KPeaaFAN2sMynSwWg4= =1yvc -----END PGP SIGNATURE----- --i9/X0Hs31jPOYl+N--