From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [13.75.44.102]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 71ED4221F1C; Thu, 2 Apr 2026 09:19:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.75.44.102 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775121562; cv=none; b=Db0o+QSSTc6W666q17+/LPqs+aOINYLZ9ZFOuxlvCQg5RasREhALK40QMYaIgmTC84xKmyYWZBYrQJ2Y30fQEjWvgYWXHvloBkAg8SYQdUyaH+0Ar+H6Ps6ehkPUjHvaAXj4Q2IHWxf8z8+p3uv1cE//mqz9two4MkH+jL/AqZU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775121562; c=relaxed/simple; bh=iulpXhrltVf5LgJaLkwZ3F9uCosclzHnWN7Mc0Tdf6s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YeQK2YbjD8sAx35xVTlzqZdEYDmy9VZj5PAHNtc76QD3noSF9kIl6+VVf4+y1G19DLZ4rMZDuXJTwOqtqnXW8PIGhGgmxcNeH33nS0KUzNeEDNeliHyQhSrw7QCLfSLsMBE5v3VxlNrNexVUV7g5LLAoYBMDaEsum0YwNhC/itI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=13.75.44.102 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0005152DT.eswin.cn (unknown [10.12.96.41]) by app1 (Coremail) with SMTP id TAJkCgA32XJ_NM5peBMOAA--.58594S2; Thu, 02 Apr 2026 17:18:57 +0800 (CST) From: dongxuyang@eswincomputing.com To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ben-linux@fluff.org, ben.dooks@codethink.co.uk, p.zabel@pengutronix.de, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, xuxiang@eswincomputing.com, wangguosheng@eswincomputing.com, pinkesh.vaghela@einfochips.com, Xuyang Dong Subject: [PATCH v3 1/2] dt-bindings: pwm: dwc: add reset optional Date: Thu, 2 Apr 2026 17:18:54 +0800 Message-Id: <20260402091854.1666-1-dongxuyang@eswincomputing.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20260402091718.1608-1-dongxuyang@eswincomputing.com> References: <20260402091718.1608-1-dongxuyang@eswincomputing.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:TAJkCgA32XJ_NM5peBMOAA--.58594S2 X-Coremail-Antispam: 1UD129KBjvJXoW7Ww4fGrW7Ww13GryUCF4UArb_yoW8Gw1DpF Z7CFW0qr4FqF15Ww4vqr1xCr1fXFn8Aa1xKr4qq3W2kan8Ga18J3y3Kw1YqFWDArZ29FW3 WFZ3uw45Zryjyr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBv14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r1q6r43MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUXJ5wUUUUU= X-CM-SenderInfo: pgrqw5xx1d0w46hv4xpqfrz1xxwl0woofrz/ From: Xuyang Dong The DesignWare PWM controller provides separate reset signals for each clock domain, as specified in the hardware documentation. Without asserting and deasserting these resets during probe, PWM outputs may remain in an undefined state after system reboot. To address this, the driver now supports an optional 'resets' property. A full reset is performed only when no PWM channel is enabled, as determined by reading the enable bit in each channel's control register. This allows safe coexistence with bootloaders that have already configured active PWM channels. Signed-off-by: Xuyang Dong --- .../devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml index 7523a89a1773..fd9f73c75121 100644 --- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml @@ -43,6 +43,9 @@ properties: - const: bus - const: timer + resets: + maxItems: 1 + snps,pwm-number: $ref: /schemas/types.yaml#/definitions/uint32 description: The number of PWM channels configured for this instance -- 2.34.1