[PATCH v1 15/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator

Changhuang Liang
2026-04-02T11:12:50Z

Add bindings for the Peripheral-1 clock and reset generator (PER1CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clock/starfive,jhb100-per1crg.yaml | 70 +++++++++++++++++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 60 ++++++++++++++++
.../dt-bindings/reset/starfive,jhb100-crg.h | 20 ++++++
3 files changed, 150 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml

diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml
new file mode 100644
index 000000000000..517c6dd2b19f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jhb100-per1crg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-1 Clock and Reset Generator
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jhb100-per1crg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PLL7
+ - description: Peripheral-1 600MHz
+ - description: Peripheral-1 800MHz
+ - description: Peripheral-1 200MHz
+ - description: Peripheral-1 143MHz
+
+ clock-names:
+ items:
+ - const: pll7
+ - const: per1_600
+ - const: per1_800
+ - const: per1_200
+ - const: per1_143
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jhb100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@11b40000 {
+ compatible = "starfive,jhb100-per1crg";
+ reg = <0x11b40000 0x1000>;
+ clocks = <&pll7>,
+ <&sys0crg 68>,
+ <&sys0crg 69>,
+ <&sys2crg 19>,
+ <&sys2crg 22>;
+ clock-names = "pll7", "per1_600",
+ "per1_800", "per1_200",
+ "per1_143";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 104f302b7103..95345d104585 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -387,4 +387,64 @@
#define JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_DMAC 339
#define JHB100_PER0CLK_MAIN_ICG_EN_TRNG 340

+/* PER1CRG clocks */
+#define JHB100_PER1CLK_100 0
+#define JHB100_PER1CLK_1 1
+#define JHB100_PER1CLK_200_DIVN0 2
+#define JHB100_PER1CLK_200_DIVN1 3
+#define JHB100_PER1CLK_200_DIVN2 4
+#define JHB100_PER1CLK_200_DIVN3 5
+#define JHB100_PER1CLK_200_CCLK_DIV 6
+
+#define JHB100_PER1CLK_SGPIO0_PCLK 15
+#define JHB100_PER1CLK_SGPIO0_DCLK 16
+#define JHB100_PER1CLK_SGPIO1_PCLK 17
+#define JHB100_PER1CLK_SGPIO1_DCLK 18
+
+#define JHB100_PER1CLK_EMMC0_BCLK 22
+
+#define JHB100_PER1CLK_EMMC0_CCLK 25
+
+#define JHB100_PER1CLK_DMAC1_1CH_CORE 29
+
+#define JHB100_PER1CLK_DMAC1_1CH_ACLK 31
+
+#define JHB100_PER1CLK_DMAC2_1CH_CORE 33
+
+#define JHB100_PER1CLK_DMAC2_1CH_ACLK 35
+
+#define JHB100_PER1CLK_DMAC3_1CH_CORE 37
+
+#define JHB100_PER1CLK_DMAC3_1CH_ACLK 39
+
+#define JHB100_PER1CLK_DMAC0_2CH_CORE 41
+
+#define JHB100_PER1CLK_DMAC0_2CH_ACLK 43
+
+#define JHB100_PER1CLK_UFS_REF 45
+#define JHB100_PER1CLK_UFS_300 46
+#define JHB100_PER1CLK_UFS_150 47
+#define JHB100_PER1CLK_UFS_400 48
+#define JHB100_PER1CLK_UFS_75 49
+#define JHB100_PER1CLK_UFS_37_5 50
+#define JHB100_PER1CLK_UFS_7_5 51
+#define JHB100_PER1CLK_UFS_1_875 52
+#define JHB100_PER1CLK_UFS_7_143 53
+#define JHB100_PER1CLK_UFS_3_5715 54
+
+#define JHB100_PER1CLK_MAIN_ICG_EN_SFC0 63
+#define JHB100_PER1CLK_MAIN_ICG_EN_SFC1 64
+#define JHB100_PER1CLK_MAIN_ICG_EN_SFC2 65
+#define JHB100_PER1CLK_MAIN_ICG_EN_SPI0 66
+#define JHB100_PER1CLK_MAIN_ICG_EN_SGPIO0 67
+#define JHB100_PER1CLK_MAIN_ICG_EN_SGPIO1 68
+#define JHB100_PER1CLK_MAIN_ICG_EN_SENSORS_PERIPH1 69
+#define JHB100_PER1CLK_MAIN_ICG_EN_EMMC0 70
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC0 71
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC1 72
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC2 73
+#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SPI0 74
+#define JHB100_PER1CLK_MAIN_ICG_EN_RAS 75
+#define JHB100_PER1CLK_MAIN_ICG_EN_UFS 76
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index bb5238cb02f6..57977d5b4018 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -143,4 +143,24 @@
#define JHB100_PER0RST_GPIO_IOMUX_PRESETN 74
#define JHB100_PER0RST_UART_MUX_REG_WRAP 75

+/* PER1CRG resets */
+#define JHB100_PER1RST_IOMUX_PRESETN 0
+#define JHB100_PER1RST_SYSCON_PRESETN 1
+#define JHB100_PER1RST_MAIN_RSTN_SFC0 2
+#define JHB100_PER1RST_MAIN_RSTN_SFC1 3
+#define JHB100_PER1RST_MAIN_RSTN_SFC2 4
+#define JHB100_PER1RST_MAIN_RSTN_SPI0 5
+#define JHB100_PER1RST_MAIN_RSTN_PERIPH1_SENSORS 6
+#define JHB100_PER1RST_MAIN_RSTN_SGPIO0 7
+#define JHB100_PER1RST_MAIN_RSTN_SGPIO1 8
+#define JHB100_PER1RST_MAIN_RSTN_EMMC0 9
+
+#define JHB100_PER1RST_MAIN_RSTN_UFS 11
+#define JHB100_PER1RST_MAIN_RSTN_UFS_PHY 12
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC0 13
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC1 14
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC2 15
+#define JHB100_PER1RST_MAIN_RSTN_DMAC_SPI0 16
+#define JHB100_PER1RST_MAIN_RSTN_PERIPH1_RAS 17
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
--
2.25.1