[PATCH v1 07/22] dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator

Changhuang Liang
2026-04-02T13:31:00Z

Add bindings for the System-1 clocks and reset generator (SYS1CRG) on
JHB100 SoC.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clock/starfive,jhb100-sys1crg.yaml | 71 +++++++++++++++++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 20 ++++++
.../dt-bindings/reset/starfive,jhb100-crg.h | 13 ++++
3 files changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml

diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml
new file mode 100644
index 000000000000..0cfeb8400b58
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jhb100-sys1crg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 System-1 Clock and Reset Generator
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jhb100-sys1crg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (25 MHz)
+ - description: PLL0
+ - description: PLL1
+ - description: PLL2
+ - description: PLL4
+ - description: PLL5
+ - description: System-1 NPU 600MHz
+
+ clock-names:
+ items:
+ - const: osc
+ - const: pll0
+ - const: pll1
+ - const: pll2
+ - const: pll4
+ - const: pll5
+ - const: sys1_npu_600
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jhb100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@13004000 {
+ compatible = "starfive,jhb100-sys1crg";
+ reg = <0x13004000 0x4000>;
+ clocks = <&osc>, <&pll0>, <&pll1>,
+ <&syspll 0>, <&syspll 2>,
+ <&syspll 3>, <&sys0crg 61>;
+ clock-names = "osc", "pll0", "pll1", "pll2",
+ "pll4", "pll5", "sys1_npu_600";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index b257cd104a10..510a5c6fa89a 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -53,4 +53,24 @@
#define JHB100_SYS0CLK_GPU0_600 73
#define JHB100_SYS0CLK_GPU1_600 74

+/* SYS1CRG clocks */
+#define JHB100_SYS1CLK_APB_MAIN_SYS1 0
+#define JHB100_SYS1CLK_APB_SENSOR_ICG_BUF 1
+
+#define JHB100_SYS1CLK_GPIO_ESPI1_66 5
+
+#define JHB100_SYS1CLK_HOSTSS1_100 7
+#define JHB100_SYS1CLK_HOSTSS1_PHY_SCAN_1000_ICG_BUF 8
+#define JHB100_SYS1CLK_NPU_200 9
+#define JHB100_SYS1CLK_NPU_CORE_DIV 10
+#define JHB100_SYS1CLK_DOM_NPU_CORE_CLK 11
+#define JHB100_SYS1CLK_DOM_NPU_BUS_CLK 12
+#define JHB100_SYS1CLK_DOM_NPU_INIT_CLK 13
+#define JHB100_SYS1CLK_DOM_NPU_OSC_CLK 14
+#define JHB100_SYS1CLK_VOUT_100 15
+#define JHB100_SYS1CLK_VOUT_PIX0 16
+#define JHB100_SYS1CLK_VOUT_PIX1 17
+#define JHB100_SYS1CLK_BMCPER3_100 18
+#define JHB100_SYS1CLK_BMCPER3_125 19
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index 71affdcdf733..9a0ab64abafa 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -27,4 +27,17 @@
#define JHB100_SYS0RST_BMCUSB_RSTN_BUS 23
#define JHB100_SYS0RST_BMCUSB_RSTN_CRG 24

+/* SYS1CRG resets */
+#define JHB100_SYS1RST_SYS1_IOMUX_PRESETN 1
+
+#define JHB100_SYS1RST_MAIN_RSTN_CHIPTOP_SENSOR 5
+
+#define JHB100_SYS1RST_VOUT_RSTN_HOST0 8
+#define JHB100_SYS1RST_VOUT_RSTN_HOST1 9
+#define JHB100_SYS1RST_HOSTSS1_RSTN_BUS_ESPI 10
+#define JHB100_SYS1RST_HOSTSS1_RSTN_BUS_PCIE 11
+#define JHB100_SYS1RST_HOSTSS1_RSTN_CRG 12
+#define JHB100_SYS1RST_BMCPERIPH3_RSTN_CRG 13
+#define JHB100_SYS1RST_BMCPERIPH3_RSTN_BUS 14
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
--
2.25.1