[PATCH v1 19/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator

Changhuang Liang
2026-04-02T12:30:30Z

Add bindings for the Peripheral-3 clock and reset generator (PER3CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clock/starfive,jhb100-per3crg.yaml | 78 +++++++++++++++++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 35 +++++++++
.../dt-bindings/reset/starfive,jhb100-crg.h | 9 +++
3 files changed, 122 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml

diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml
new file mode 100644
index 000000000000..5043e97d2f28
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jhb100-per3crg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-3 Clock and Reset Generator
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jhb100-per3crg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Peripheral-3 600MHz
+ - description: Peripheral-3 100MHz
+ - description: Peripheral-3 125MHz
+ - description: Peripheral-3 GMAC0 RMII Reference clock
+ - description: Peripheral-3 GMAC1 SGMII TX
+ - description: Peripheral-3 GMAC1 SGMII RX
+ - description: Main Oscillator (25 MHz)
+
+ clock-names:
+ items:
+ - const: per3_600
+ - const: per3_100
+ - const: per3_125
+ - const: per3_gmac0_rmii_rclki
+ - const: per3_gmac1_sgmii_tx
+ - const: per3_gmac1_sgmii_rx
+ - const: osc
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jhb100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@11c40000 {
+ compatible = "starfive,jhb100-per3crg";
+ reg = <0x11c40000 0x1000>;
+ clocks = <&sys0crg 65>,
+ <&sys1crg 18>,
+ <&sys1crg 19>,
+ <&per3_gmac0_rmii_rclki>,
+ <&per3_gmac1_sgmii_tx>,
+ <&per3_gmac1_sgmii_rx>,
+ <&osc>;
+ clock-names = "per3_600", "per3_100", "per3_125",
+ "per3_gmac0_rmii_rclki",
+ "per3_gmac1_sgmii_tx",
+ "per3_gmac1_sgmii_rx",
+ "osc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 2ab505437118..6b7d53a0391a 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -504,4 +504,39 @@
#define JHB100_PER2CLK_MAIN_ICG_EN_GMAC2 69
#define JHB100_PER2CLK_MAIN_ICG_EN_GMAC3 70

+/* PER3CRG clocks */
+#define JHB100_PER3CLK_300 0
+#define JHB100_PER3CLK_200 1
+#define JHB100_PER3CLK_GMAC1_PTP_REF 2
+#define JHB100_PER3CLK_GMAC1_TX_125_MUX 3
+#define JHB100_PER3CLK_GMAC1_TX 4
+#define JHB100_PER3CLK_GMAC1_RX_125_MUX 5
+#define JHB100_PER3CLK_GMAC1_RX 6
+#define JHB100_PER3CLK_GMAC0_PTP_REF 7
+#define JHB100_PER3CLK_GMAC0_RMII_PLL 8
+#define JHB100_PER3CLK_GMAC0_RMII_MUX 9
+#define JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2 10
+
+#define JHB100_PER3CLK_ETHER0_RMII_CLK_TX_I 17
+#define JHB100_PER3CLK_ETHER0_RMII_CLK_RX_I 18
+#define JHB100_PER3CLK_ETHER0_RMII_CLK_PTP_REF_I 19
+#define JHB100_PER3CLK_ETHER0_RMII_CLK_RMII_I 20
+#define JHB100_PER3CLK_ETHER0_RMII_CLK_CSR_I 21
+#define JHB100_PER3CLK_ETHER0_RMII_ACLK_I 22
+#define JHB100_PER3CLK_GMAC0_RMII_RCLKO 23
+#define JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_I 24
+#define JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_I 25
+#define JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_125_I 26
+#define JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_125_I 27
+#define JHB100_PER3CLK_ETHER0_SGMII_CLK_PTP_REF_I 28
+#define JHB100_PER3CLK_ETHER0_SGMII_CLK_REF_25_I 29
+#define JHB100_PER3CLK_ETHER0_SGMII_CLK_CSR_I 30
+#define JHB100_PER3CLK_ETHER0_SGMII_ACLK_I 31
+#define JHB100_PER3CLK_ETHER0_SGMII_PHY_PCLK_I 32
+#define JHB100_PER3CLK_MAIN_ICG_EN_SENSORS_PERIPH3 33
+#define JHB100_PER3CLK_MAIN_ICG_EN_PECI0 34
+#define JHB100_PER3CLK_MAIN_ICG_EN_PECI1 35
+#define JHB100_PER3CLK_MAIN_ICG_EN_GMAC0 36
+#define JHB100_PER3CLK_MAIN_ICG_EN_GMAC1 37
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index 102af1042903..4b15e348e92f 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -181,4 +181,13 @@
#define JHB100_PER2RST_ADC1_IOMUX_PRESETN 14
#define JHB100_PER2RST_MAIN_RSTN_PERIPH2_SENSORS 15

+/* PER3CRG resets */
+#define JHB100_PER3RST_SYSREG_RSTN 0
+#define JHB100_PER3RST_MAIN_RSTN_GMAC0 1
+#define JHB100_PER3RST_MAIN_RSTN_GMAC1 2
+#define JHB100_PER3RST_MAIN_RSTN_PECI0 3
+#define JHB100_PER3RST_MAIN_RSTN_PECI1 4
+#define JHB100_PER3RST_MAIN_RSTN_PERIPH3_SENSORS 5
+#define JHB100_PER3RST_IOMUX_PRESETN 6
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
--
2.25.1