Re: [PATCH v1 05/22] dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator

Changhuang Liang
2026-04-03T01:26:35Z

> On Do, 2026-04-02 at 03:55 -0700, Changhuang Liang wrote:
> > Add bindings for the System-0 clocks and reset generator (SYS0CRG) on
> > JHB100 SoC.
> >
> > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> > ---
> > .../clock/starfive,jhb100-sys0crg.yaml | 63
> +++++++++++++++++++
> > .../dt-bindings/clock/starfive,jhb100-crg.h | 56 +++++++++++++++++
> > .../dt-bindings/reset/starfive,jhb100-crg.h | 30 +++++++++
> > 3 files changed, 149 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml
> > create mode 100644 include/dt-bindings/clock/starfive,jhb100-crg.h
> > create mode 100644 include/dt-bindings/reset/starfive,jhb100-crg.h
> >
> [...]
> > diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h
> > b/include/dt-bindings/reset/starfive,jhb100-crg.h
> > new file mode 100644
> > index 000000000000..71affdcdf733
> > --- /dev/null
> > +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
> > @@ -0,0 +1,30 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> > +/*
> > + * Copyright (C) 2024 StarFive Technology Co., Ltd.
> > + * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
> > + *
> > + */
> > +
> > +#ifndef __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__
> > +#define __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__
> > +
> > +/* SYS0CRG resets */
> > +#define JHB100_SYS0RST_RESOURCE_ARB 0
>
> Where are resets 1 and 2, ...
>
> > +#define JHB100_SYS0RST_SYS0_IOMUX_PRESETN 3
> > +#define JHB100_SYS0RST_SYS0H_IOMUX_PRESETN 4
> > +#define JHB100_SYS0RST_RST_ADAPTOR_TIMEOUT_RSTN
> 5
>
> ... where are 6-13?
>
> > +
> > +#define JHB100_SYS0RST_BMCPCIERP_RSTN_BUS 14
> [...]
>
> If there are non-reset bits in these registers, please enumerate reset controls
> in a contiguous range for this binding and add a mapping table in the driver.
>

I will do this.

Best Regards,
Changhuang