[PATCH v1 06/22] clk: starfive: Add JHB100 System-0 clock generator driver

Changhuang Liang
2026-04-02T11:14:08Z

Add support for JHB100 System-0 clock generator (SYS0CRG).

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 7 +
drivers/clk/starfive/Kconfig | 11 +
drivers/clk/starfive/Makefile | 2 +
.../clk/starfive/clk-starfive-jhb100-sys0.c | 253 ++++++++++++++++++
drivers/clk/starfive/clk-starfive-jhb100.h | 11 +
5 files changed, 284 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0.c
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100.h

diff --git a/MAINTAINERS b/MAINTAINERS
index b1892a480c31..3af9d79b7daf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25306,6 +25306,13 @@ S: Supported
F: Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
F: drivers/irqchip/irq-starfive-jh8100-intc.c

+STARFIVE JHB100 CLOCK DRIVERS
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: Documentation/devicetree/bindings/clock/starfive,jhb1*.yaml
+F: drivers/clk/starfive/clk-starfive-jhb1*
+F: include/dt-bindings/clock/starfive,jhb1*.h
+
STARFIVE JHB100 DEVICETREES
M: Changhuang Liang <changhuang.liang@starfivetech.com>
L: linux-riscv@lists.infradead.org
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index ff8eace36e64..7926e02ccd7d 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -72,3 +72,14 @@ config CLK_STARFIVE_JH7110_VOUT
help
Say yes here to support the Video-Output clock controller
on the StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JHB100_SYS0
+ bool "StarFive JHB100 system-0 clock support"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select AUXILIARY_BUS
+ select CLK_STARFIVE_COMMON
+ select RESET_STARFIVE_JHB100 if RESET_CONTROLLER
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the system-0 clock controller on the
+ StarFive JHB100 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 012f7ee83f8e..2c5e66d1d44e 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -10,3 +10,5 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
+
+obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys0.c b/drivers/clk/starfive/clk-starfive-jhb100-sys0.c
new file mode 100644
index 000000000000..00299b161e2b
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-sys0.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 System-0 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/auxiliary_bus.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <soc/starfive/reset-starfive-common.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_SYS0CLK_NUM_CLKS (JHB100_SYS0CLK_GPU1_600 + 1)
+
+/* external clocks */
+#define JHB100_SYS0CLK_OSC (JHB100_SYS0CLK_NUM_CLKS + 0)
+#define JHB100_SYS0CLK_PLL0 (JHB100_SYS0CLK_NUM_CLKS + 1)
+#define JHB100_SYS0CLK_PLL1 (JHB100_SYS0CLK_NUM_CLKS + 2)
+#define JHB100_SYS0CLK_PLL2 (JHB100_SYS0CLK_NUM_CLKS + 3)
+
+static const struct starfive_clk_data jhb100_sys0crg_clk_data[] __initconst = {
+ /* bmcpcierp */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPCIERP_600, "bmcpcierp_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPCIERP_100, "bmcpcierp_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_PCIE_REF_CML, "pcie_ref_cml", 24,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_DATA_INIT, "bmcpcierp_ncnoc_data_init",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_600),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG_INIT, "bmcpcierp_ncnoc_cfg_init",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_100),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_NCNOC_TARG, "bmcpcierp_ncnoc_targ",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCPCIERP_600),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCPCIERP_PCU, "bmcpcierp_pcu",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_OSC),
+ /* hostss0 */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS0_100, "hostss0_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS0_600, "hostss0_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS0_PHY_SCAN_400, "hostss0_phy_scan_400", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_GPIO_ESPI0_66, "gpio_espi0_66", 14,
+ JHB100_SYS0CLK_PLL2),
+ /* bmcusb */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCUSB_600, "bmcusb_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCUSB_200, "bmcusb_200", 6,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCUSB_SCANCLK, "bmcusb_scanclk", 5,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE_GATE(JHB100_SYS0CLK_BMCUSB_480M_SCANCLK, "bmcusb_480m_scanclk",
+ CLK_IS_CRITICAL, JHB100_SYS0CLK_BMCUSB_SCANCLK),
+ /* vce */
+ STARFIVE__DIV(JHB100_SYS0CLK_VCE_600, "vce_600", 10,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_VCE_100, "vce_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ /* bmcperiph2 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_600, "bmcper2_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_100, "bmcper2_100", 12,
+ JHB100_SYS0CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_400, "bmcper2_400", 8,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER2_125, "bmcper2_125", 10,
+ JHB100_SYS0CLK_PLL1),
+ /* hostss1 */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS1_600, "hostss1_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400, "hostss1_phy_scan_400", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE_GATE(JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400_ICG_BUF,
+ "hostss1_phy_scan_400_icg_buf", CLK_IS_CRITICAL,
+ JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400),
+ /* npu */
+ STARFIVE__DIV(JHB100_SYS0CLK_NPU_600, "npu_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* vout */
+ STARFIVE__DIV(JHB100_SYS0CLK_VOUT_600, "vout_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_VOUT_AUX, "vout_aux", 150,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph3 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER3_600, "bmcper3_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* hostusb */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTUSB_600, "hostusb_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ /* hostusbcmn */
+ STARFIVE__DIV(JHB100_SYS0CLK_HOSTUSBCMN_480, "hostusbcmn_480", 5,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph1 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER1_600, "bmcper1_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER1_800, "bmcper1_800", 4,
+ JHB100_SYS0CLK_PLL0),
+ /* bmcperiph0 */
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER0_600, "bmcper0_600", 6,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER0_400, "bmcper0_400", 8,
+ JHB100_SYS0CLK_PLL0),
+ STARFIVE__DIV(JHB100_SYS0CLK_BMCPER0_800, "bmcper0_800", 8,
+ JHB100_SYS0CLK_PLL0),
+ /* gpu0 */
+ STARFIVE__DIV(JHB100_SYS0CLK_GPU0_600, "gpu0_600", 10,
+ JHB100_SYS0CLK_PLL0),
+ /* gpu1 */
+ STARFIVE__DIV(JHB100_SYS0CLK_GPU1_600, "gpu1_600", 10,
+ JHB100_SYS0CLK_PLL0),
+};
+
+static void jhb100_reset_unregister_adev(void *_adev)
+{
+ struct auxiliary_device *adev = _adev;
+
+ auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
+}
+
+static void jhb100_reset_adev_release(struct device *dev)
+{
+ struct auxiliary_device *adev = to_auxiliary_dev(dev);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
+
+ kfree(rdev);
+}
+
+int jhb100_reset_controller_register(struct starfive_clk_priv *priv,
+ const char *adev_name,
+ u32 adev_id)
+{
+ struct starfive_reset_adev *rdev;
+ struct auxiliary_device *adev;
+ int ret;
+
+ rdev = kzalloc_obj(*rdev);
+ if (!rdev)
+ return -ENOMEM;
+
+ rdev->base = priv->base;
+
+ adev = &rdev->adev;
+ adev->name = adev_name;
+ adev->dev.parent = priv->dev;
+ adev->dev.release = jhb100_reset_adev_release;
+ adev->id = adev_id;
+
+ ret = auxiliary_device_init(adev);
+ if (ret)
+ return ret;
+
+ ret = auxiliary_device_add(adev);
+ if (ret) {
+ auxiliary_device_uninit(adev);
+ return ret;
+ }
+
+ return devm_add_action_or_reset(priv->dev,
+ jhb100_reset_unregister_adev, adev);
+}
+EXPORT_SYMBOL_GPL(jhb100_reset_controller_register);
+
+static int __init jhb100_sys0crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_SYS0CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_SYS0CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_SYS0CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_sys0crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_sys0crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_sys0crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_sys0crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_SYS0CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_SYS0CLK_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JHB100_SYS0CLK_PLL0)
+ parents[i].fw_name = "pll0";
+ else if (pidx == JHB100_SYS0CLK_PLL1)
+ parents[i].fw_name = "pll1";
+ else
+ parents[i].fw_name = "pll2";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-sys0", 0);
+}
+
+static const struct of_device_id jhb100_sys0crg_match[] = {
+ { .compatible = "starfive,jhb100-sys0crg" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jhb100_sys0crg_driver = {
+ .driver = {
+ .name = "clk-starfive-jhb100-sys0",
+ .of_match_table = jhb100_sys0crg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jhb100_sys0crg_driver, jhb100_sys0crg_probe);
diff --git a/drivers/clk/starfive/clk-starfive-jhb100.h b/drivers/clk/starfive/clk-starfive-jhb100.h
new file mode 100644
index 000000000000..6c5cb3e9c610
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CLK_STARFIVE_JHB100_H
+#define __CLK_STARFIVE_JHB100_H
+
+#include "clk-starfive-common.h"
+
+int jhb100_reset_controller_register(struct starfive_clk_priv *priv,
+ const char *adev_name,
+ u32 adev_id);
+
+#endif
--
2.25.1