[PATCH v1 16/22] clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver

Changhuang Liang
2026-04-02T11:14:23Z

Add driver for the StarFive JHB100 Peripheral-1 clock controller.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-per1.c | 204 ++++++++++++++++++
3 files changed, 213 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per1.c

diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index adf97444f460..72cf314c6cfc 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -81,6 +81,14 @@ config CLK_STARFIVE_JHB100_PER0
Say yes here to support the peripheral-0 clock controller
on the StarFive JHB100 SoC.

+config CLK_STARFIVE_JHB100_PER1
+ bool "StarFive JHB100 peripheral-1 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS2
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the peripheral-1 clock controller
+ on the StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 2f605d0fd6da..51511086a727 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o

obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per1.c b/drivers/clk/starfive/clk-starfive-jhb100-per1.c
new file mode 100644
index 000000000000..c5c1cff5d9a8
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-per1.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 Peripheral-1 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_PER1CLK_NUM_CLKS (JHB100_PER1CLK_MAIN_ICG_EN_UFS + 1)
+
+/* external clocks */
+#define JHB100_PER1CLK_143 (JHB100_PER1CLK_NUM_CLKS + 0)
+#define JHB100_PER1CLK_200 (JHB100_PER1CLK_NUM_CLKS + 1)
+#define JHB100_PER1CLK_600 (JHB100_PER1CLK_NUM_CLKS + 2)
+#define JHB100_PER1CLK_800 (JHB100_PER1CLK_NUM_CLKS + 3)
+#define JHB100_PER1CLK_PLL7 (JHB100_PER1CLK_NUM_CLKS + 4)
+
+static const struct starfive_clk_data jhb100_per1crg_clk_data[] = {
+ STARFIVE__DIV(JHB100_PER1CLK_100, "per1_100", 8, JHB100_PER1CLK_600),
+ STARFIVE__DIV(JHB100_PER1CLK_1, "per1_1", 100, JHB100_PER1CLK_100),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN0, "200_divn0", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN1, "200_divn1", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN2, "200_divn2", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_DIVN3, "200_divn3", 256,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_200_CCLK_DIV, "200_cclk_div", 2046,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO0_PCLK, "sgpio0_pclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO0_DCLK, "sgpio0_dclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO1_PCLK, "sgpio1_pclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_SGPIO1_DCLK, "sgpio1_dclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_EMMC0_BCLK, "emmc0_bclk", CLK_IGNORE_UNUSED,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_EMMC0_CCLK, "emmc0_cclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC1_1CH_CORE, "dmac1_1ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC1_1CH_ACLK, "dmac1_1ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC2_1CH_CORE, "dmac2_1ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC2_1CH_ACLK, "dmac2_1ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC3_1CH_CORE, "dmac3_1ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC3_1CH_ACLK, "dmac3_1ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC0_2CH_CORE, "dmac0_2ch_core", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_DMAC0_2CH_ACLK, "dmac0_2ch_aclk", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_REF, "ufs_ref", 75,
+ JHB100_PER1CLK_PLL7),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_300, "ufs_300", 2,
+ JHB100_PER1CLK_600),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_150, "ufs_150", 12,
+ JHB100_PER1CLK_600),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_400, "ufs_400", 2,
+ JHB100_PER1CLK_800),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_75, "ufs_75", 2,
+ JHB100_PER1CLK_UFS_150),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_37_5, "ufs_37_5", 2,
+ JHB100_PER1CLK_UFS_75),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_7_5, "ufs_7_5", 10,
+ JHB100_PER1CLK_UFS_75),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_1_875, "ufs_1_875", 4,
+ JHB100_PER1CLK_UFS_7_5),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_7_143, "ufs_7_143", 20,
+ JHB100_PER1CLK_143),
+ STARFIVE__DIV(JHB100_PER1CLK_UFS_3_5715, "ufs_3_5715", 2,
+ JHB100_PER1CLK_UFS_7_143),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC0, "main_icg_en_sfc0", CLK_IS_CRITICAL,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC1, "main_icg_en_sfc1", CLK_IS_CRITICAL,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC2, "main_icg_en_sfc2", CLK_IS_CRITICAL,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SPI0, "main_icg_en_spi0", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_EMMC0, "main_icg_en_emmc0", 0,
+ JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SGPIO0, "main_icg_en_sgpio0", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SGPIO1, "main_icg_en_sgpio1", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SENSORS_PERIPH1, "main_icg_en_sensors_periph1", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC0, "main_icg_en_dmac_sfc0",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC1, "main_icg_en_dmac_sfc1",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC2, "main_icg_en_dmac_sfc2",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SPI0, "main_icg_en_dmac_spi0",
+ CLK_IS_CRITICAL, JHB100_PER1CLK_200),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_RAS, "main_icg_en_ras", 0,
+ JHB100_PER1CLK_100),
+ STARFIVE_GATE(JHB100_PER1CLK_MAIN_ICG_EN_UFS, "main_icg_en_ufs", 0,
+ JHB100_PER1CLK_100),
+};
+
+static int jhb100_per1crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_PER1CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_PER1CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_PER1CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_per1crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_per1crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_per1crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_per1crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_PER1CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_PER1CLK_600)
+ parents[i].fw_name = "per1_600";
+ else if (pidx == JHB100_PER1CLK_200)
+ parents[i].fw_name = "per1_200";
+ else if (pidx == JHB100_PER1CLK_800)
+ parents[i].fw_name = "per1_800";
+ else if (pidx == JHB100_PER1CLK_143)
+ parents[i].fw_name = "per1_143";
+ else if (pidx == JHB100_PER1CLK_PLL7)
+ parents[i].fw_name = "pll7";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-per1", 0);
+}
+
+static const struct of_device_id jhb100_per1crg_match[] = {
+ { .compatible = "starfive,jhb100-per1crg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per1crg_match);
+
+static struct platform_driver jhb100_per1crg_driver = {
+ .probe = jhb100_per1crg_probe,
+ .driver = {
+ .name = "clk-starfive-jhb100-per1",
+ .of_match_table = jhb100_per1crg_match,
+ },
+};
+module_platform_driver(jhb100_per1crg_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 Peripheral-1 Clock Driver");
+MODULE_LICENSE("GPL");
--
2.25.1