From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93B4D31690A; Thu, 2 Apr 2026 13:13:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775135624; cv=none; b=L+k6EekyIGUK8HKWDipn7pN2sKTw4QElZhBDDgKczkaC/SyfBJF2Mj8aefe27Ntw7CSEEbsBZcm13MRmo8m7WtVeDEaatJwhJ+upUKt2hQQsAebvFbeCwNd+UIKPzhirAGFvonk3S4Sm1tg7H87munJFqcJHpANRBnUgoA7Tmjg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775135624; c=relaxed/simple; bh=olJG/w5hEVxAxRdsneJR6SiqNQrFbJh9xOCQLGWReYk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JnlX4hnhX1awhabnmsIDZGZK5LgRM9/v/sTMOyAC1gLt7S6j3wjQkCdnmaHYz8FBW4J41M/6HW4wM66wrFr0EGt581CR0B6o1MhPdxiLlK1kwj98SfUM1ZnxsxAqpzhdb3lSbVWcg7eLECY+n+Ap3WLqC18PJAgAIq025nwSCPc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=rrH/mWEE; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="rrH/mWEE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1775135624; x=1806671624; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=olJG/w5hEVxAxRdsneJR6SiqNQrFbJh9xOCQLGWReYk=; b=rrH/mWEEtgRNCZ+KTewmx6gtZNCIZBfgboGhpLDNwFoRVypGsrm+BN6F rn8Pnxt1MH/8tf1uSOHTS5uaEtVzffo8W1b2MmvAW1DPZUHMfmy1TrATG MuOxd7ENOmHCFUSTndzcNxH2MIi5kGTZS2cJoFPYPi0VDzZ8p5mHgS3Qk Sv6GUVPy91eVk+KyZ+Vx/BEBfox+7v0ffrSoYmgsY2PheorriZ95X7gBv b9X983j/k7Z4k3O7jWikCywLlhaZUH/jiw0dlGyGYIN5LbKCCu/LmUAQL p6u/gx4MBH3RxM6itP9wQhtuvu7+2m3wJ9lZzrleA5N/2fggWdw6W2spW w==; X-CSE-ConnectionGUID: UGofO4cJSXOAkJsSzS2N8A== X-CSE-MsgGUID: tLTeN27nTTi6FCeQooa60w== X-IronPort-AV: E=Sophos;i="6.23,155,1770620400"; d="scan'208";a="55583668" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2026 06:13:43 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Thu, 2 Apr 2026 06:13:08 -0700 Received: from bby-cbu-swbuild03.eng.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Thu, 2 Apr 2026 06:13:08 -0700 From: Charles Perry To: CC: Charles Perry , Andrew Lunn , "David S. Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , Subject: [PATCH net-next v4 1/3] dt-bindings: net: document Microchip PIC64-HPSC/HX MDIO controller Date: Thu, 2 Apr 2026 06:12:22 -0700 Message-ID: <20260402131229.319599-2-charles.perry@microchip.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260402131229.319599-1-charles.perry@microchip.com> References: <20260402131229.319599-1-charles.perry@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain This MDIO hardware is based on a Microsemi design supported in Linux by mdio-mscc-miim.c. However, The register interface is completely different with pic64hpsc, hence the need for separate documentation. The hardware supports C22 and C45. The documentation recommends an input clock of 156.25MHz and a prescaler of 39, which yields an MDIO clock of 1.95MHz. The hardware supports an interrupt pin to signal transaction completion which is not strictly needed as the software can also poll a "TRIGGER" bit for this. Signed-off-by: Charles Perry --- Notes: Changes in v4: none Changes in v3: none Changes in v2: - Make "clocks" and "interrupts" required (Andrew) - Add a default value to "clock-frequency" (Andrew) .../net/microchip,pic64hpsc-mdio.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml diff --git a/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml b/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml new file mode 100644 index 000000000000..d690afe3d3cf --- /dev/null +++ b/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/microchip,pic64hpsc-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC64-HPSC/HX MDIO controller + +maintainers: + - Charles Perry + +description: | + Microchip PIC64-HPSC/HX SoCs have two MDIO bus controller. This MDIO bus + controller supports C22 and C45 register access. It is named "MDIO Initiator" + in the documentation. + +allOf: + - $ref: mdio.yaml# + +properties: + compatible: + oneOf: + - const: microchip,pic64hpsc-mdio + - items: + - const: microchip,pic64hx-mdio + - const: microchip,pic64hpsc-mdio + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + default: 2500000 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + bus { + #address-cells = <2>; + #size-cells = <2>; + + mdio@4000C21E000 { + compatible = "microchip,pic64hpsc-mdio"; + reg = <0x400 0x0C21E000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&svc_clk>; + interrupt-parent = <&saplic0>; + interrupts = <168 IRQ_TYPE_LEVEL_HIGH>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; -- 2.47.3