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From: Conor Dooley <conor@kernel.org>
To: Changhuang Liang <changhuang.liang@starfivetech.com>
Cc: Emil Renner Berthing <kernel@esmil.dk>,
	Joel Stanley <jms@oss.tenstorrent.com>,
	Drew Fustini <dfustini@oss.tenstorrent.com>,
	Darshan Prajapati <darshan.prajapati@einfochips.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>, Rob Herring <robh@kernel.org>,
	Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,
	Hal Feng <hal.feng@starfivetech.com>,
	Guodong Xu <guodong@riscstar.com>, Yixun Lan <dlan@kernel.org>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Albert Ou <aou@eecs.berkeley.edu>, E Shattow <e@freeshell.de>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>,
	Junhui Liu <junhui.liu@pigmoral.tech>,
	Daniel Lezcano <daniel.lezcano@kernel.org>,
	Michal Simek <michal.simek@amd.com>,
	Paul Walmsley <pjw@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Samuel Holland <samuel.holland@sifive.com>,
	Michael Zhu <michael.zhu@starfivetech.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Thomas Gleixner <tglx@kernel.org>,
	JiSheng Teoh <jisheng.teoh@starfivetech.com>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>
Subject: Re: [PATCH v1 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT
Date: Fri, 3 Apr 2026 09:49:42 +0100	[thread overview]
Message-ID: <20260403-pristine-slam-71d8e0093b6f@spud> (raw)
In-Reply-To: <ZQ4PR01MB1202CB8B853CA7E03531914BF25E2@ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn>

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On Fri, Apr 03, 2026 at 03:06:23AM +0000, Changhuang Liang wrote:
> Hi, Conor
> 
> > On Thu, Apr 02, 2026 at 01:40:19AM -0700, Changhuang Liang wrote:
> > > From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > >
> > > Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT,
> > > PLIC, PMU, UART and 1GB DDR.
> > >
> > > Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> > > ---
> > >  MAINTAINERS                                   |   6 +
> > >  arch/riscv/boot/dts/starfive/Makefile         |   2 +
> > >  .../boot/dts/starfive/jhb100-evb1-eth.dts     |   6 +
> > >  arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi |  32 ++
> > >  arch/riscv/boot/dts/starfive/jhb100.dtsi      | 326
> > ++++++++++++++++++
> > >  5 files changed, 372 insertions(+)
> > >  create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > >  create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> > >  create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
> > >
> > > diff --git a/MAINTAINERS b/MAINTAINERS index
> > > 7d10988cbc62..b1892a480c31 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -25306,6 +25306,12 @@ S:	Supported
> > >  F:
> > 	Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100
> > -intc.yaml
> > >  F:	drivers/irqchip/irq-starfive-jh8100-intc.c
> > >
> > > +STARFIVE JHB100 DEVICETREES
> > > +M:	Changhuang Liang <changhuang.liang@starfivetech.com>
> > > +L:	linux-riscv@lists.infradead.org
> > > +S:	Maintained
> > 
> > Supported, no?
> > 
> > > +F:	arch/riscv/boot/dts/starfive/jhb100*
> > > +
> > >  STATIC BRANCH/CALL
> > >  M:	Peter Zijlstra <peterz@infradead.org>
> > >  M:	Josh Poimboeuf <jpoimboe@kernel.org>
> > > diff --git a/arch/riscv/boot/dts/starfive/Makefile
> > > b/arch/riscv/boot/dts/starfive/Makefile
> > > index 3dd1f05283f7..7cdb75788053 100644
> > > --- a/arch/riscv/boot/dts/starfive/Makefile
> > > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > > @@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > jh7110-starfive-visionfive-2-lite.dtb
> > >  dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > jh7110-starfive-visionfive-2-lite-emmc.dtb
> > >  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> > >  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> > > +
> > > +dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1-eth.dtb
> > > diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > new file mode 100644
> > > index 000000000000..62cd046e1224
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > @@ -0,0 +1,6 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> > > + */
> > > +
> > > +#include "jhb100-evb1.dtsi"
> > 
> > What is the point of this file? Is this the base-board?
> > Shouldn't it have a specific compatible?
> > 
> > Can the SoM be used without a base board? I've got no info about this board
> > appearing on google, do you even have pictures of it or any documentation?
> > I see this
> > https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=22
> > and
> > https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=23
> > but the former doesn't look like it needs a base-board and the latter is called
> > "evb3", so is not what's here?
> 
> The former is the base board of the EVB1. Currently, we are only carrying out 
> upstream work based on the EVB1. The EVB1 base board has reserved slots 

Except when I look at the first link, the picture doesn't show something
that is a SoM + base-board, it's just a regular board. If that's the
case, the breakdown of files doesn't make sense, with jhb100-evb1.dtsi
sounding like it should be a dts. Usually we talk about base-boards in
relation to a SoM, like what the mars-cm needs to function.



> that can accommodate expansion boards to verify more advanced features. 
> At present, the jhb100-evb1.dtsi file corresponds to the configuration of the 
> EVB1 base board. In the future, we will add dtsi files for the expansion boards. 
> The jhb100-evb1-eth.dts file will then be used to combine these dtsi files to 
> generate the final version of the device tree source.

Sounds like here the evb1 is a complete board and jhb100-evb1-eth.dts
represents some kind of expansion card added to that board? 
I think this not correct, since the base-board needs to be usable in
isolation. Take a look at what rockchip do for rk3588-rock-5b-pcie-ep
in arch/arm64/boot/dts/rockchip/Makefile/, where these expansion type
things are dealt with using overlays.

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      reply	other threads:[~2026-04-03  8:49 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-02  8:40 [PATCH v1 0/5] Initial device tree support for StarFive JHB100 SoC Changhuang Liang
2026-04-02  8:40 ` [PATCH v1 1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles Changhuang Liang
2026-04-02  8:40 ` [PATCH v1 2/5] dt-bindings: timer: Add StarFive JHB100 clint Changhuang Liang
2026-04-02  8:40 ` [PATCH v1 3/5] dt-bindings: interrupt-controller: Add StarFive JHB100 plic Changhuang Liang
2026-04-02  8:40 ` [PATCH v1 4/5] dt-bindings: riscv: Add StarFive JHB100 SoC Changhuang Liang
2026-04-02  8:40 ` [PATCH v1 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT Changhuang Liang
2026-04-02 12:25   ` Conor Dooley
2026-04-03  3:06     ` Changhuang Liang
2026-04-03  8:49       ` Conor Dooley [this message]

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