[PATCH v1 0/5] Initial device tree support for StarFive JHB100 SoC

[PATCH v1 0/5] Initial device tree support for StarFive JHB100 SoC

[Changhuang Liang]

StarFive JHB100 SoC consists of 4 RISC-V low power Cores (Dubhe-70). It
also features various interfaces such as I2C, SPI, CAN, USB, MMC, Uart,
etc.

This patch series introduces initial SoC DTSI support for the StarFive
JHB100 SoC. The relevant dt-binding documentation has been updated
accordingly. Below is the list of IP blocks added in the initial SoC DTSI.

- StarFive Dubhe-70 CPU
- PMU
- PLIC
- CLINT
- UART

This patch series is based on tag 7.0-rc5 and has been tested on the
StarFive JHB100 EVB-1.

Ji Sheng Teoh (1):
  dt-bindings: riscv: Add StarFive Dubhe-70 compatibles

Ley Foon Tan (4):
  dt-bindings: timer: Add StarFive JHB100 clint
  dt-bindings: interrupt-controller: Add StarFive JHB100 plic
  dt-bindings: riscv: Add StarFive JHB100 SoC
  riscv: dts: starfive: jhb100: Add JHB100 base DT

 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../devicetree/bindings/riscv/cpus.yaml       |   1 +
 .../devicetree/bindings/riscv/starfive.yaml   |   5 +
 .../bindings/timer/sifive,clint.yaml          |   1 +
 MAINTAINERS                                   |   6 +
 arch/riscv/boot/dts/starfive/Makefile         |   2 +
 .../boot/dts/starfive/jhb100-evb1-eth.dts     |   6 +
 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi |  32 ++
 arch/riscv/boot/dts/starfive/jhb100.dtsi      | 326 ++++++++++++++++++
 9 files changed, 380 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi


base-commit: c369299895a591d96745d6492d4888259b004a9e
prerequisite-patch-id: 5735e71493da6858decc510a0e75967744b66b39
--
2.25.1

[PATCH v1 1/5] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles

[Changhuang Liang]

From: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>

Add new compatible string for Dubhe-70.
Dubhe-70 is a low power RISC-V cpu core from StarFive Technology.

Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 5feeb2203050..e7eda7a9c345 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,7 @@ properties:
               - sifive,u74-mc
               - spacemit,x100
               - spacemit,x60
+              - starfive,dubhe-70
               - thead,c906
               - thead,c908
               - thead,c910
-- 
2.25.1

[PATCH v1 2/5] dt-bindings: timer: Add StarFive JHB100 clint

[Changhuang Liang]

From: Ley Foon Tan <leyfoon.tan@starfivetech.com>

Add compatible string for the StarFive JHB100 clint.

Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 3bab40500df9..387086bc6b5e 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -37,6 +37,7 @@ properties:
               - starfive,jh7100-clint   # StarFive JH7100
               - starfive,jh7110-clint   # StarFive JH7110
               - starfive,jh8100-clint   # StarFive JH8100
+              - starfive,jhb100-clint   # StarFive JHB100
               - tenstorrent,blackhole-clint # Tenstorrent Blackhole
           - const: sifive,clint0        # SiFive CLINT v0 IP block
       - items:
-- 
2.25.1

[PATCH v1 3/5] dt-bindings: interrupt-controller: Add StarFive JHB100 plic

[Changhuang Liang]

From: Ley Foon Tan <leyfoon.tan@starfivetech.com>

Add compatible string for StarFive JHB100 plic.

Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index e0267223887e..49d63100bf87 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,7 @@ properties:
               - spacemit,k1-plic
               - starfive,jh7100-plic
               - starfive,jh7110-plic
+              - starfive,jhb100-plic
               - tenstorrent,blackhole-plic
           - const: sifive,plic-1.0.0
       - items:
-- 
2.25.1

[PATCH v1 4/5] dt-bindings: riscv: Add StarFive JHB100 SoC

[Changhuang Liang]

From: Ley Foon Tan <leyfoon.tan@starfivetech.com>

Add device tree bindings for the StarFive JHB100 RISC-V SoC.

Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 8ba0e10b529a..277618efff6e 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -43,6 +43,11 @@ properties:
           - const: starfive,jh7110s
           - const: starfive,jh7110
 
+      - items:
+          - enum:
+              - starfive,jhb100-evb1
+          - const: starfive,jhb100
+
 additionalProperties: true
 
 ...
-- 
2.25.1

[PATCH v1 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT

[Changhuang Liang]

From: Ley Foon Tan <leyfoon.tan@starfivetech.com>

Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT, PLIC,
PMU, UART and 1GB DDR.

Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 MAINTAINERS                                   |   6 +
 arch/riscv/boot/dts/starfive/Makefile         |   2 +
 .../boot/dts/starfive/jhb100-evb1-eth.dts     |   6 +
 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi |  32 ++
 arch/riscv/boot/dts/starfive/jhb100.dtsi      | 326 ++++++++++++++++++
 5 files changed, 372 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index 7d10988cbc62..b1892a480c31 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25306,6 +25306,12 @@ S:	Supported
 F:	Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
 F:	drivers/irqchip/irq-starfive-jh8100-intc.c
 
+STARFIVE JHB100 DEVICETREES
+M:	Changhuang Liang <changhuang.liang@starfivetech.com>
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+F:	arch/riscv/boot/dts/starfive/jhb100*
+
 STATIC BRANCH/CALL
 M:	Peter Zijlstra <peterz@infradead.org>
 M:	Josh Poimboeuf <jpoimboe@kernel.org>
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 3dd1f05283f7..7cdb75788053 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
+
+dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1-eth.dtb
diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
new file mode 100644
index 000000000000..62cd046e1224
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
+ */
+
+#include "jhb100-evb1.dtsi"
diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
new file mode 100644
index 000000000000..462b6fb7953b
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
+ */
+
+#include "jhb100.dtsi"
+
+/ {
+	model = "StarFive JHB100 EVB-1";
+	compatible = "starfive,jhb100-evb1", "starfive,jhb100";
+
+	aliases {
+		serial6 = &uart6;
+	};
+
+	chosen {
+		stdout-path = "serial6:115200n8";
+	};
+
+	cpus {
+		timebase-frequency = <5000000>;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x0 0x40000000>;	/* 1GB */
+	};
+};
+
+&uart6 {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
new file mode 100644
index 000000000000..4d03470f78ab
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "starfive,jhb100";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "starfive,dubhe-70", "riscv";
+			riscv,isa = "rv64imafdcbh";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+					       "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintpause",
+					       "zihpm", "svinval", "svnapot", "sscofpmf";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <512>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <16>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <512>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <24>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2c0>;
+			reg = <0x0>;
+			tlb-split;
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu1: cpu@1 {
+			compatible = "starfive,dubhe-70", "riscv";
+			riscv,isa = "rv64imafdcbh";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+					       "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintpause",
+					       "zihpm", "svinval", "svnapot", "sscofpmf";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <512>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <16>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <512>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <24>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2c1>;
+			reg = <0x1>;
+			tlb-split;
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu2: cpu@2 {
+			compatible = "starfive,dubhe-70", "riscv";
+			riscv,isa = "rv64imafdcbh";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+					       "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintpause",
+					       "zihpm", "svinval", "svnapot", "sscofpmf";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <512>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <16>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <512>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <24>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2c2>;
+			reg = <0x2>;
+			tlb-split;
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu3: cpu@3 {
+			compatible = "starfive,dubhe-70", "riscv";
+			riscv,isa = "rv64imafdcbh";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
+					       "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
+					       "zicond", "zicsr", "zifencei", "zihintpause",
+					       "zihpm", "svinval", "svnapot", "sscofpmf";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <512>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <16>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <512>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <24>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2c3>;
+			reg = <0x3>;
+			tlb-split;
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu1>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&cpu2>;
+				};
+			};
+
+			cluster3 {
+				core0 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		l2c0: cache-controller-0 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <0x20000>;
+			cache-unified;
+			next-level-cache = <&l3_cache>;
+		};
+
+		l2c1: cache-controller-1 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <0x20000>;
+			cache-unified;
+			next-level-cache = <&l3_cache>;
+		};
+
+		l2c2: cache-controller-2 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <0x20000>;
+			cache-unified;
+			next-level-cache = <&l3_cache>;
+		};
+
+		l2c3: cache-controller-3 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <0x20000>;
+			cache-unified;
+			next-level-cache = <&l3_cache>;
+		};
+
+		l3_cache: cache-controller-4 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <3>;
+			cache-sets = <1024>;
+			cache-size = <0x20000>;
+			cache-unified;
+		};
+	};
+
+	pmu {
+		compatible = "riscv,pmu";
+		interrupts-extended = <&cpu0_intc 13>, <&cpu1_intc 13>,
+				      <&cpu2_intc 13>, <&cpu3_intc 13>;
+
+		riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>,
+					   <0x00006 0x0000 0xB>,
+					   <0x00008 0x0000 0x10>,
+					   <0x00009 0x0000 0xF>,
+					   <0x10000 0x0000 0x19>,
+					   <0x10001 0x0000 0x1A>,
+					   <0x10002 0x0000 0x1B>,
+					   <0x10003 0x0000 0x1C>,
+					   <0x10008 0x0000 0x8>,
+					   <0x10009 0x0000 0x9>,
+					   <0x1000C 0x0000 0x9E>,
+					   <0x1000D 0x0000 0x9F>,
+					   <0x10010 0x0000 0x1D>,
+					   <0x10011 0x0000 0x1E>,
+					   <0x10012 0x0000 0x1F>,
+					   <0x10013 0x0000 0x20>,
+					   <0x10014 0x0000 0x21>,
+					   <0x10018 0x0000 0x17>,
+					   <0x10019 0x0000 0x18>,
+					   <0x10020 0x0000 0x8>,
+					   <0x10021 0x0000 0x7>;
+
+		riscv,event-to-mhpmcounters = <0x00005 0x00006 0x00007FF8>,
+					      <0x00008 0x00009 0x00007FF8>,
+					      <0x10000 0x10003 0x00007FF8>,
+					      <0x10008 0x10009 0x00007FF8>,
+					      <0x1000C 0x1000D 0x00007FF8>,
+					      <0x10010 0x10014 0x00007FF8>,
+					      <0x10018 0x10019 0x00007FF8>,
+					      <0x10020 0x10021 0x00007FF8>;
+
+		riscv,raw-event-to-mhpmcounters =
+			<0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>,	/* Event ID 1-31 */
+			<0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>,	/* Event ID 32-33 */
+			<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>;	/* Event ID 34 */
+	};
+
+	clk_uart: clk-uart {
+		compatible = "fixed-clock"; /* Initial clock handler for UART */
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clint: timer@2000000 {
+			compatible = "starfive,jhb100-clint", "sifive,clint0";
+			reg = <0x0 0x02000000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>;
+		};
+
+		plic: interrupt-controller@c000000 {
+			compatible = "starfive,jhb100-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0x0c000000 0x0 0x4000000>;
+			riscv,ndev = <400>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>;
+		};
+
+		bus_nioc: bus_nioc {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-noncoherent;
+			dma-ranges = <0x4 0x00000000 0x0 0x40000000 0x2 0x0>,
+				     <0x4 0x00000000 0x4 0x00000000 0x2 0x0>;
+			ranges;
+
+			uart6: serial@11982000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x0 0x11982000 0x0 0x400>;
+				clocks = <&clk_uart>, <&clk_uart>;
+				clock-names = "baudclk", "apb_pclk";
+				reg-io-width = <4>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
2.25.1

Re: [PATCH v1 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT

[Conor Dooley]

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On Thu, Apr 02, 2026 at 01:40:19AM -0700, Changhuang Liang wrote:
> From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> 
> Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT, PLIC,
> PMU, UART and 1GB DDR.
> 
> Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
>  MAINTAINERS                                   |   6 +
>  arch/riscv/boot/dts/starfive/Makefile         |   2 +
>  .../boot/dts/starfive/jhb100-evb1-eth.dts     |   6 +
>  arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi |  32 ++
>  arch/riscv/boot/dts/starfive/jhb100.dtsi      | 326 ++++++++++++++++++
>  5 files changed, 372 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
>  create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
>  create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7d10988cbc62..b1892a480c31 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -25306,6 +25306,12 @@ S:	Supported
>  F:	Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
>  F:	drivers/irqchip/irq-starfive-jh8100-intc.c
>  
> +STARFIVE JHB100 DEVICETREES
> +M:	Changhuang Liang <changhuang.liang@starfivetech.com>
> +L:	linux-riscv@lists.infradead.org
> +S:	Maintained

Supported, no?

> +F:	arch/riscv/boot/dts/starfive/jhb100*
> +
>  STATIC BRANCH/CALL
>  M:	Peter Zijlstra <peterz@infradead.org>
>  M:	Josh Poimboeuf <jpoimboe@kernel.org>
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 3dd1f05283f7..7cdb75788053 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> +
> +dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1-eth.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> new file mode 100644
> index 000000000000..62cd046e1224
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> + */
> +
> +#include "jhb100-evb1.dtsi"

What is the point of this file? Is this the base-board?
Shouldn't it have a specific compatible?

Can the SoM be used without a base board? I've got no info about this
board appearing on google, do you even have pictures of it or any
documentation?
I see this
https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=22
and
https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=23
but the former doesn't look like it needs a base-board and the latter is
called "evb3", so is not what's here?

Not got enough info to really do any kind of review here.

> diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> new file mode 100644
> index 000000000000..462b6fb7953b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> + */
> +
> +#include "jhb100.dtsi"
> +
> +/ {
> +	model = "StarFive JHB100 EVB-1";
> +	compatible = "starfive,jhb100-evb1", "starfive,jhb100";
> +
> +	aliases {
> +		serial6 = &uart6;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial6:115200n8";
> +	};
> +
> +	cpus {
> +		timebase-frequency = <5000000>;
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x40000000 0x0 0x40000000>;	/* 1GB */
> +	};
> +};
> +
> +&uart6 {
> +	status = "okay";
> +};

> +		cpu2: cpu@2 {
> +			compatible = "starfive,dubhe-70", "riscv";
> +			riscv,isa = "rv64imafdcbh";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
> +					       "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
> +					       "zicond", "zicsr", "zifencei", "zihintpause",
> +					       "zihpm", "svinval", "svnapot", "sscofpmf";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			d-cache-block-size = <64>;
> +			d-cache-sets = <512>;
> +			d-cache-size = <32768>;
> +			d-tlb-sets = <1>;
> +			d-tlb-size = <16>;
> +			device_type = "cpu";
> +			i-cache-block-size = <64>;
> +			i-cache-sets = <512>;
> +			i-cache-size = <32768>;
> +			i-tlb-sets = <1>;
> +			i-tlb-size = <24>;
> +			mmu-type = "riscv,sv48";
> +			next-level-cache = <&l2c2>;
> +			reg = <0x2>;

reg after compatible please.

> +			tlb-split;
> +
> +			cpu2_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};

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Re: [PATCH v1 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT

[Changhuang Liang]

Hi, Conor

> On Thu, Apr 02, 2026 at 01:40:19AM -0700, Changhuang Liang wrote:
> > From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> >
> > Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT,
> > PLIC, PMU, UART and 1GB DDR.
> >
> > Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> > ---
> >  MAINTAINERS                                   |   6 +
> >  arch/riscv/boot/dts/starfive/Makefile         |   2 +
> >  .../boot/dts/starfive/jhb100-evb1-eth.dts     |   6 +
> >  arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi |  32 ++
> >  arch/riscv/boot/dts/starfive/jhb100.dtsi      | 326
> ++++++++++++++++++
> >  5 files changed, 372 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> >  create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> >  create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS index
> > 7d10988cbc62..b1892a480c31 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -25306,6 +25306,12 @@ S:	Supported
> >  F:
> 	Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100
> -intc.yaml
> >  F:	drivers/irqchip/irq-starfive-jh8100-intc.c
> >
> > +STARFIVE JHB100 DEVICETREES
> > +M:	Changhuang Liang <changhuang.liang@starfivetech.com>
> > +L:	linux-riscv@lists.infradead.org
> > +S:	Maintained
> 
> Supported, no?
> 
> > +F:	arch/riscv/boot/dts/starfive/jhb100*
> > +
> >  STATIC BRANCH/CALL
> >  M:	Peter Zijlstra <peterz@infradead.org>
> >  M:	Josh Poimboeuf <jpoimboe@kernel.org>
> > diff --git a/arch/riscv/boot/dts/starfive/Makefile
> > b/arch/riscv/boot/dts/starfive/Makefile
> > index 3dd1f05283f7..7cdb75788053 100644
> > --- a/arch/riscv/boot/dts/starfive/Makefile
> > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > @@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) +=
> > jh7110-starfive-visionfive-2-lite.dtb
> >  dtb-$(CONFIG_ARCH_STARFIVE) +=
> > jh7110-starfive-visionfive-2-lite-emmc.dtb
> >  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> >  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> > +
> > +dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1-eth.dtb
> > diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > new file mode 100644
> > index 000000000000..62cd046e1224
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > @@ -0,0 +1,6 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> > + */
> > +
> > +#include "jhb100-evb1.dtsi"
> 
> What is the point of this file? Is this the base-board?
> Shouldn't it have a specific compatible?
> 
> Can the SoM be used without a base board? I've got no info about this board
> appearing on google, do you even have pictures of it or any documentation?
> I see this
> https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=22
> and
> https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=23
> but the former doesn't look like it needs a base-board and the latter is called
> "evb3", so is not what's here?

The former is the base board of the EVB1. Currently, we are only carrying out 
upstream work based on the EVB1. The EVB1 base board has reserved slots 
that can accommodate expansion boards to verify more advanced features. 
At present, the jhb100-evb1.dtsi file corresponds to the configuration of the 
EVB1 base board. In the future, we will add dtsi files for the expansion boards. 
The jhb100-evb1-eth.dts file will then be used to combine these dtsi files to 
generate the final version of the device tree source.

Best Regards,
Changhuang

Re: [PATCH v1 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT

[Conor Dooley]

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On Fri, Apr 03, 2026 at 03:06:23AM +0000, Changhuang Liang wrote:
> Hi, Conor
> 
> > On Thu, Apr 02, 2026 at 01:40:19AM -0700, Changhuang Liang wrote:
> > > From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > >
> > > Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT,
> > > PLIC, PMU, UART and 1GB DDR.
> > >
> > > Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> > > ---
> > >  MAINTAINERS                                   |   6 +
> > >  arch/riscv/boot/dts/starfive/Makefile         |   2 +
> > >  .../boot/dts/starfive/jhb100-evb1-eth.dts     |   6 +
> > >  arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi |  32 ++
> > >  arch/riscv/boot/dts/starfive/jhb100.dtsi      | 326
> > ++++++++++++++++++
> > >  5 files changed, 372 insertions(+)
> > >  create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > >  create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> > >  create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
> > >
> > > diff --git a/MAINTAINERS b/MAINTAINERS index
> > > 7d10988cbc62..b1892a480c31 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -25306,6 +25306,12 @@ S:	Supported
> > >  F:
> > 	Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100
> > -intc.yaml
> > >  F:	drivers/irqchip/irq-starfive-jh8100-intc.c
> > >
> > > +STARFIVE JHB100 DEVICETREES
> > > +M:	Changhuang Liang <changhuang.liang@starfivetech.com>
> > > +L:	linux-riscv@lists.infradead.org
> > > +S:	Maintained
> > 
> > Supported, no?
> > 
> > > +F:	arch/riscv/boot/dts/starfive/jhb100*
> > > +
> > >  STATIC BRANCH/CALL
> > >  M:	Peter Zijlstra <peterz@infradead.org>
> > >  M:	Josh Poimboeuf <jpoimboe@kernel.org>
> > > diff --git a/arch/riscv/boot/dts/starfive/Makefile
> > > b/arch/riscv/boot/dts/starfive/Makefile
> > > index 3dd1f05283f7..7cdb75788053 100644
> > > --- a/arch/riscv/boot/dts/starfive/Makefile
> > > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > > @@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > jh7110-starfive-visionfive-2-lite.dtb
> > >  dtb-$(CONFIG_ARCH_STARFIVE) +=
> > > jh7110-starfive-visionfive-2-lite-emmc.dtb
> > >  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> > >  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> > > +
> > > +dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1-eth.dtb
> > > diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > new file mode 100644
> > > index 000000000000..62cd046e1224
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > > @@ -0,0 +1,6 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> > > + */
> > > +
> > > +#include "jhb100-evb1.dtsi"
> > 
> > What is the point of this file? Is this the base-board?
> > Shouldn't it have a specific compatible?
> > 
> > Can the SoM be used without a base board? I've got no info about this board
> > appearing on google, do you even have pictures of it or any documentation?
> > I see this
> > https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=22
> > and
> > https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=23
> > but the former doesn't look like it needs a base-board and the latter is called
> > "evb3", so is not what's here?
> 
> The former is the base board of the EVB1. Currently, we are only carrying out 
> upstream work based on the EVB1. The EVB1 base board has reserved slots 

Except when I look at the first link, the picture doesn't show something
that is a SoM + base-board, it's just a regular board. If that's the
case, the breakdown of files doesn't make sense, with jhb100-evb1.dtsi
sounding like it should be a dts. Usually we talk about base-boards in
relation to a SoM, like what the mars-cm needs to function.



> that can accommodate expansion boards to verify more advanced features. 
> At present, the jhb100-evb1.dtsi file corresponds to the configuration of the 
> EVB1 base board. In the future, we will add dtsi files for the expansion boards. 
> The jhb100-evb1-eth.dts file will then be used to combine these dtsi files to 
> generate the final version of the device tree source.

Sounds like here the evb1 is a complete board and jhb100-evb1-eth.dts
represents some kind of expansion card added to that board? 
I think this not correct, since the base-board needs to be usable in
isolation. Take a look at what rockchip do for rk3588-rock-5b-pcie-ep
in arch/arm64/boot/dts/rockchip/Makefile/, where these expansion type
things are dealt with using overlays.

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