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From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Stephen Boyd <sboyd@kernel.org>, Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Emil Renner Berthing <kernel@esmil.dk>
Cc: Chen Wang <unicorn_wang@outlook.com>,
	Inochi Amaoto <inochiama@gmail.com>,
	Alexey Charkov <alchark@gmail.com>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Keguang Zhang <keguang.zhang@gmail.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	Ley Foon Tan <leyfoon.tan@starfivetech.com>,
	Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v1 09/13] reset: starfive: Introduce assert_polarity
Date: Thu,  2 Apr 2026 22:49:41 -0700	[thread overview]
Message-ID: <20260403054945.467700-10-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>

The JHB100 SoC supports inverted operations for reset
assertion/deassertion, introducing the an assert_polarity field to
distinguish between different operation logics.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 .../reset/starfive/reset-starfive-common.c    | 51 +++++++++++++++++--
 .../reset/starfive/reset-starfive-common.h    |  5 ++
 2 files changed, 53 insertions(+), 3 deletions(-)

diff --git a/drivers/reset/starfive/reset-starfive-common.c b/drivers/reset/starfive/reset-starfive-common.c
index 772bdf6763d1..61d69cef4bc9 100644
--- a/drivers/reset/starfive/reset-starfive-common.c
+++ b/drivers/reset/starfive/reset-starfive-common.c
@@ -20,6 +20,12 @@ struct starfive_reset {
 	spinlock_t lock;
 	void __iomem *assert;
 	void __iomem *status;
+
+	/* If assert_polarity is false, setting the bit to 1 asserts
+	 * the signal while clearing it to 0 deasserts it, and vice
+	 * versa.
+	 */
+	bool assert_polarity;
 	const u32 *asserted;
 };
 
@@ -42,7 +48,7 @@ static int starfive_reset_update(struct reset_controller_dev *rcdev,
 	unsigned long flags;
 	int ret;
 
-	if (!assert)
+	if (data->assert_polarity == assert)
 		done ^= mask;
 
 	spin_lock_irqsave(&data->lock, flags);
@@ -64,13 +70,25 @@ static int starfive_reset_update(struct reset_controller_dev *rcdev,
 static int starfive_reset_assert(struct reset_controller_dev *rcdev,
 				 unsigned long id)
 {
-	return starfive_reset_update(rcdev, id, true);
+	struct starfive_reset *data = starfive_reset_from(rcdev);
+	bool assert = false;
+
+	if (!data->assert_polarity)
+		assert = true;
+
+	return starfive_reset_update(rcdev, id, assert);
 }
 
 static int starfive_reset_deassert(struct reset_controller_dev *rcdev,
 				   unsigned long id)
 {
-	return starfive_reset_update(rcdev, id, false);
+	struct starfive_reset *data = starfive_reset_from(rcdev);
+	bool deassert = false;
+
+	if (data->assert_polarity)
+		deassert = true;
+
+	return starfive_reset_update(rcdev, id, deassert);
 }
 
 static int starfive_reset_reset(struct reset_controller_dev *rcdev,
@@ -132,3 +150,30 @@ int reset_starfive_register(struct device *dev, struct device_node *of_node,
 	return devm_reset_controller_register(dev, &data->rcdev);
 }
 EXPORT_SYMBOL_GPL(reset_starfive_register);
+
+int reset_starfive_register_polarity(struct device *dev, struct device_node *of_node,
+				     void __iomem *assert, void __iomem *status,
+				     const u32 *asserted, unsigned int nr_resets,
+				     struct module *owner)
+{
+	struct starfive_reset *data;
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->rcdev.ops = &starfive_reset_ops;
+	data->rcdev.owner = owner;
+	data->rcdev.nr_resets = nr_resets;
+	data->rcdev.dev = dev;
+	data->rcdev.of_node = of_node;
+
+	spin_lock_init(&data->lock);
+	data->assert = assert;
+	data->status = status;
+	data->assert_polarity = true;
+	data->asserted = asserted;
+
+	return devm_reset_controller_register(dev, &data->rcdev);
+}
+EXPORT_SYMBOL_GPL(reset_starfive_register_polarity);
diff --git a/drivers/reset/starfive/reset-starfive-common.h b/drivers/reset/starfive/reset-starfive-common.h
index 83461b22ee55..bad56613deb9 100644
--- a/drivers/reset/starfive/reset-starfive-common.h
+++ b/drivers/reset/starfive/reset-starfive-common.h
@@ -11,4 +11,9 @@ int reset_starfive_register(struct device *dev, struct device_node *of_node,
 			    const u32 *asserted, unsigned int nr_resets,
 			    struct module *owner);
 
+int reset_starfive_register_polarity(struct device *dev, struct device_node *of_node,
+				     void __iomem *assert, void __iomem *status,
+				     const u32 *asserted, unsigned int nr_resets,
+				     struct module *owner);
+
 #endif /* __RESET_STARFIVE_COMMON_H */
-- 
2.25.1


  parent reply	other threads:[~2026-04-03  5:50 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-03  5:49 [PATCH v1 00/13] Add StarFive JHB100 syscon modules Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 01/13] dt-bindings: soc: starfive: " Changhuang Liang
2026-04-05  7:17   ` Krzysztof Kozlowski
2026-04-07  7:34     ` Changhuang Liang
2026-04-07  7:37       ` Krzysztof Kozlowski
2026-04-03  5:49 ` [PATCH v1 02/13] dt-bindings: clock: Add system-0 domain PLL clock Changhuang Liang
2026-04-05  7:18   ` Krzysztof Kozlowski
2026-04-07  6:56     ` Changhuang Liang
2026-04-07  7:02       ` Krzysztof Kozlowski
2026-04-03  5:49 ` [PATCH v1 03/13] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-04-03 16:10   ` Brian Masney
2026-04-07  1:17     ` Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 04/13] dt-bindings: clock: Add peripheral-0 domain PLL clock Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 05/13] clk: starfive: Add peripheral-0 domain PLL clock driver Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 06/13] dt-bindings: clock: Add peripheral-1 domain PLL clock Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 07/13] clk: starfive: Add Peripheral-1 domain PLL clock driver Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 08/13] dt-bindings: reset: Add StarFive JHB100 reset generator Changhuang Liang
2026-04-03  5:49 ` Changhuang Liang [this message]
2026-04-03  5:49 ` [PATCH v1 10/13] reset: starfive: Add syscon reset driver support Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 11/13] dt-bindings: hwinfo: Add starfive,jhb100-socinfo Changhuang Liang
2026-04-05  7:19   ` Krzysztof Kozlowski
2026-04-07  6:49     ` Changhuang Liang
2026-04-07  7:06       ` Krzysztof Kozlowski
2026-04-03  5:49 ` [PATCH v1 12/13] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
2026-04-07 15:43   ` Conor Dooley
2026-04-07 15:47   ` Conor Dooley
2026-04-03  5:49 ` [PATCH v1 13/13] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
2026-04-05  7:18 ` [PATCH v1 00/13] Add StarFive JHB100 syscon modules Krzysztof Kozlowski

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