[PATCH v1 04/13] dt-bindings: clock: Add peripheral-0 domain PLL clock

Changhuang Liang
2026-04-03T05:50:12Z

Add peripheral-0 domain PLL clock for StarFive JHB100 SoC.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../devicetree/bindings/clock/starfive,jhb100-pll.yaml | 1 +
include/dt-bindings/clock/starfive,jhb100-crg.h | 3 +++
2 files changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
index f7ab90c05281..920fde5e1b0a 100644
--- a/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
@@ -18,6 +18,7 @@ properties:
compatible:
enum:
- starfive,jhb100-sys0-pll
+ - starfive,jhb100-per0-pll

clocks:
maxItems: 1
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 719a6eb9b1a4..55e91ede977e 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -14,6 +14,9 @@
#define JHB100_SYS0PLL_PLL4_OUT 2
#define JHB100_SYS0PLL_PLL5_OUT 3

+/* PER0PLL clocks */
+#define JHB100_PER0PLL_PLL6_OUT 0
+
/* SYS0CRG clocks */
#define JHB100_SYS0CLK_BMCPCIERP_600 17
#define JHB100_SYS0CLK_BMCPCIERP_100 18
--
2.25.1