[PATCH v1 02/13] dt-bindings: clock: Add system-0 domain PLL clock

Changhuang Liang
2026-04-03T05:50:10Z

Add system-0 domain PLL clock for StarFive JHB100 SoC.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../bindings/clock/starfive,jhb100-pll.yaml | 44 +++++++++++++++++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 6 +++
2 files changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml

diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
new file mode 100644
index 000000000000..f7ab90c05281
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jhb100-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 PLL Clock Generator
+
+description:
+ These PLLs are high speed, low jitter frequency synthesizers in the JHB100.
+ Each PLL works in integer mode or fraction mode, with configuration
+ registers in the syscon. So the PLLs node should be a child of SYSCON node.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ enum:
+ - starfive,jhb100-sys0-pll
+
+ clocks:
+ maxItems: 1
+ description: Main Oscillator (25 MHz)
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller {
+ compatible = "starfive,jhb100-sys0-pll";
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 6b7d53a0391a..719a6eb9b1a4 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -8,6 +8,12 @@
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__

+/* SYS0PLL clocks */
+#define JHB100_SYS0PLL_PLL2_OUT 0
+#define JHB100_SYS0PLL_PLL3_OUT 1
+#define JHB100_SYS0PLL_PLL4_OUT 2
+#define JHB100_SYS0PLL_PLL5_OUT 3
+
/* SYS0CRG clocks */
#define JHB100_SYS0CLK_BMCPCIERP_600 17
#define JHB100_SYS0CLK_BMCPCIERP_100 18
--
2.25.1