Re: [PATCH v1 02/13] dt-bindings: clock: Add system-0 domain PLL clock

Krzysztof Kozlowski
2026-04-07T07:02:34Z

On 07/04/2026 08:56, Changhuang Liang wrote:
> Hi, Krzysztof
>
> Thanks for the review.
>
>> On Thu, Apr 02, 2026 at 10:49:34PM -0700, Changhuang Liang wrote:
>>> Add system-0 domain PLL clock for StarFive JHB100 SoC.
>>>
>>> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
>>> ---
>>> .../bindings/clock/starfive,jhb100-pll.yaml | 44 +++++++++++++++++++
>>> .../dt-bindings/clock/starfive,jhb100-crg.h | 6 +++
>>
>> You did not test your code. Apply patch #1 and test it. Do you see build-level
>> errors?
>
> I'm very sorry about this. I will reorganize my patch to avoid the related errors.
>

Anyway this one should be folded into the parent. You have one generic,
system-wide clock as input, so as well this can be the resource of the
parent. And no address spaces.

Other examples have one-register address spaces, so these are not really
separate devices.

Best regards,
Krzysztof