[PATCH v1 05/13] clk: starfive: Add peripheral-0 domain PLL clock driver

Changhuang Liang
2026-04-03T05:50:14Z

Add peripheral-0 domain PLL clock driver support for StarFive JHB100
SoC.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clk/starfive/clk-starfive-jhb100-pll.c | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)

diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
index 1751a734ee83..5fddb07d0d13 100644
--- a/drivers/clk/starfive/clk-starfive-jhb100-pll.c
+++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
@@ -27,6 +27,9 @@
#define JHB100_PLL4_OFFSET 0x18
#define JHB100_PLL5_OFFSET 0x24

+/* Peripheral-0 domain PLL */
+#define JHB100_PLL6_OFFSET 0x00
+
#define JHB100_PLL_CFG0_OFFSET 0x0
#define JHB100_PLL_CFG1_OFFSET 0x4
#define JHB100_PLL_CFG2_OFFSET 0x8
@@ -479,10 +482,35 @@ static const struct jhb100_pll_match_data jhb100_sys0_pll = {
.num_pll = ARRAY_SIZE(jhb100_sys0_pll_info),
};

+static const struct jhb100_pll_preset jhb100_pll6_presets[] = {
+ {
+ .freq = 2400000000,
+ .fbdiv = 192,
+ .frac = 0,
+ .refdiv = 1,
+ .postdiv = 0,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ },
+};
+
+static const struct jhb100_pll_info jhb100_per0_pll_info[] = {
+ JHB100_PLL(JHB100_PER0PLL_PLL6_OUT, "pll6_out", jhb100_pll6_presets,
+ ARRAY_SIZE(jhb100_pll6_presets), JHB100_PLL6_OFFSET, false),
+};
+
+static const struct jhb100_pll_match_data jhb100_per0_pll = {
+ .pll_info = jhb100_per0_pll_info,
+ .num_pll = ARRAY_SIZE(jhb100_per0_pll_info),
+};
+
static const struct of_device_id jhb100_pll_match[] = {
{
.compatible = "starfive,jhb100-sys0-pll",
.data = (void *)&jhb100_sys0_pll,
+ }, {
+ .compatible = "starfive,jhb100-per0-pll",
+ .data = (void *)&jhb100_per0_pll,
}, {
/* sentinel */
}
--
2.25.1