[PATCH v1 07/13] clk: starfive: Add Peripheral-1 domain PLL clock driver

Changhuang Liang
2026-04-03T05:50:16Z

Add Peripheral-1 domain PLL clock driver support for StarFive JHB100 SoC.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clk/starfive/clk-starfive-jhb100-pll.c | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)

diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
index 5fddb07d0d13..522d920a3353 100644
--- a/drivers/clk/starfive/clk-starfive-jhb100-pll.c
+++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
@@ -30,6 +30,9 @@
/* Peripheral-0 domain PLL */
#define JHB100_PLL6_OFFSET 0x00

+/* Peripheral-1 domain PLL */
+#define JHB100_PLL7_OFFSET 0x40
+
#define JHB100_PLL_CFG0_OFFSET 0x0
#define JHB100_PLL_CFG1_OFFSET 0x4
#define JHB100_PLL_CFG2_OFFSET 0x8
@@ -504,6 +507,28 @@ static const struct jhb100_pll_match_data jhb100_per0_pll = {
.num_pll = ARRAY_SIZE(jhb100_per0_pll_info),
};

+static const struct jhb100_pll_preset jhb100_pll7_presets[] = {
+ {
+ .freq = 1950000000,
+ .fbdiv = 156,
+ .frac = 0,
+ .refdiv = 1,
+ .postdiv = 0,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ },
+};
+
+static const struct jhb100_pll_info jhb100_per1_pll_info[] = {
+ JHB100_PLL(JHB100_PER1PLL_PLL7_OUT, "pll7_out", jhb100_pll7_presets,
+ ARRAY_SIZE(jhb100_pll7_presets), JHB100_PLL7_OFFSET, false),
+};
+
+static const struct jhb100_pll_match_data jhb100_per1_pll = {
+ .pll_info = jhb100_per1_pll_info,
+ .num_pll = ARRAY_SIZE(jhb100_per1_pll_info),
+};
+
static const struct of_device_id jhb100_pll_match[] = {
{
.compatible = "starfive,jhb100-sys0-pll",
@@ -511,6 +536,9 @@ static const struct of_device_id jhb100_pll_match[] = {
}, {
.compatible = "starfive,jhb100-per0-pll",
.data = (void *)&jhb100_per0_pll,
+ }, {
+ .compatible = "starfive,jhb100-per1-pll",
+ .data = (void *)&jhb100_per1_pll,
}, {
/* sentinel */
}
--
2.25.1