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Fri, 3 Apr 2026 05:50:17 +0000 From: Changhuang Liang To: Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Philipp Zabel , Emil Renner Berthing Cc: Chen Wang , Inochi Amaoto , Alexey Charkov , Thomas Bogendoerfer , Keguang Zhang , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Ley Foon Tan , Changhuang Liang Subject: [PATCH v1 13/13] riscv: dts: starfive: jhb100: Add syscon nodes Date: Thu, 2 Apr 2026 22:49:45 -0700 Message-Id: <20260403054945.467700-14-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com> References: <20260403054945.467700-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: BJXPR01CA0052.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:12::19) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1252:EE_ X-MS-Office365-Filtering-Correlation-Id: 82bf2bc6-db10-4d69-7d2e-08de9144e1ff X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|52116014|7416014|376014|921020|38350700014|56012099003|22082099003|18002099003; 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They contain pcieep0_ecsr_syscon | host0_syscon | husb0_syscon | husbd0_syscon | pcieep1_ecsr_syscon | host1_syscon | husb1_syscon | husbd1_syscon | gpu0_syscon | gpu1_syscon | husbcmn_syscon | b2h0_syscon | b2h1_syscon | h02b_syscon | h12b_syscon | vout_syscon | pcierp_ecsr_syscon | pcierp_syscon | usb_syscon | npu_syscon | per0_syscon | per1_syscon | per2_syscon | per3_syscon | sys0_syscon | sys1_syscon | sys2_syscon | strap_syscon. Simultaneously add the pll, reset, and chipid nodes under syscon. Also update the references of pll nodes. Signed-off-by: Changhuang Liang --- arch/riscv/boot/dts/starfive/jhb100.dtsi | 220 +++++++++++++++++++---- 1 file changed, 186 insertions(+), 34 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi index 700d00f800bc..3456aef30500 100644 --- a/arch/riscv/boot/dts/starfive/jhb100.dtsi +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi @@ -288,36 +288,6 @@ pll1: pll1 { clock-frequency = <1000000000>; }; - pll2: pll2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <903168000>; - }; - - pll4: pll4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100700000>; - }; - - pll5: pll5 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100700000>; - }; - - pll6: pll6 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2400000000>; - }; - - pll7: pll7 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1950000000>; - }; - per2_gmac2_rgmii_rx: per2-gmac2-rgmii-rx { compatible = "fixed-clock"; #clock-cells = <0>; @@ -398,6 +368,116 @@ bus_nioc: bus_nioc { <0x4 0x00000000 0x4 0x00000000 0x2 0x0>; ranges; + pcieep0_ecsr_syscon: syscon@10511000 { + compatible = "starfive,jhb100-pcieep-ecsr-syscon", "syscon"; + reg = <0x0 0x10511000 0x0 0x1000>; + }; + + host0_syscon: syscon@10519000 { + compatible = "starfive,jhb100-host-syscon", "syscon"; + reg = <0x0 0x10519000 0x0 0x1000>; + }; + + husb0_syscon: syscon@10695000 { + compatible = "starfive,jhb100-husb-syscon", "syscon"; + reg = <0x0 0x10695000 0x0 0x800>; + }; + + husbd0_syscon: syscon@10695800 { + compatible = "starfive,jhb100-husbd-syscon", "syscon"; + reg = <0x0 0x10695800 0x0 0x800>; + }; + + gpu0_syscon: syscon@10745000 { + compatible = "starfive,jhb100-gpu-syscon", "syscon"; + reg = <0x0 0x10745000 0x0 0x1000>; + }; + + pcieep1_ecsr_syscon: syscon@10d11000 { + compatible = "starfive,jhb100-pcieep-ecsr-syscon", "syscon"; + reg = <0x0 0x10d11000 0x0 0x1000>; + }; + + host1_syscon: syscon@10d19000 { + compatible = "starfive,jhb100-host-syscon", "syscon"; + reg = <0x0 0x10d19000 0x0 0x1000>; + }; + + husb1_syscon: syscon@10e95000 { + compatible = "starfive,jhb100-husb-syscon", "syscon"; + reg = <0x0 0x10e95000 0x0 0x800>; + }; + + husbd1_syscon: syscon@10e95800 { + compatible = "starfive,jhb100-husbd-syscon", "syscon"; + reg = <0x0 0x10e95800 0x0 0x800>; + }; + + gpu1_syscon: syscon@10f45000 { + compatible = "starfive,jhb100-gpu-syscon", "syscon"; + reg = <0x0 0x10f45000 0x0 0x1000>; + }; + + husbcmn_syscon: syscon@11045000 { + compatible = "starfive,jhb100-husbcmn-syscon", "syscon"; + reg = <0x0 0x11045000 0x0 0x1000>; + }; + + b2h0_syscon: syscon@11135000 { + compatible = "starfive,jhb100-b2h-syscon", "syscon"; + reg = <0x0 0x11135000 0x0 0x200>; + }; + + b2h1_syscon: syscon@11135200 { + compatible = "starfive,jhb100-b2h-syscon", "syscon"; + reg = <0x0 0x11135200 0x0 0x200>; + }; + + h02b_syscon: syscon@11135400 { + compatible = "starfive,jhb100-h2b-syscon", "syscon"; + reg = <0x0 0x11135400 0x0 0x100>; + }; + + h12b_syscon: syscon@11135500 { + compatible = "starfive,jhb100-h2b-syscon", "syscon"; + reg = <0x0 0x11135500 0x0 0x100>; + }; + + vout_syscon: syscon@11135800 { + compatible = "starfive,jhb100-vout-syscon", "syscon"; + reg = <0x0 0x11135800 0x0 0x400>; + }; + + pcierp_ecsr_syscon: syscon@11711000 { + compatible = "starfive,jhb100-pcierp-ecsr-syscon", "syscon"; + reg = <0x0 0x11711000 0x0 0x1000>; + }; + + pcierp_syscon: syscon@11719000 { + compatible = "starfive,jhb100-pcierp-syscon", "syscon", + "simple-mfd"; + reg = <0x0 0x11719000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x11719000 0x0 0x1000>; + + pcierp_syscon_rst: reset-controller@14c { + compatible = "starfive,jhb100-reset-pcierp"; + reg = <0x0 0x14c 0x0 0x4>; + #reset-cells = <1>; + }; + }; + + usb_syscon: syscon@11820000 { + compatible = "starfive,jhb100-usb-syscon", "syscon"; + reg = <0x0 0x11820000 0x0 0x10000>; + }; + + npu_syscon: syscon@118e5000 { + compatible = "starfive,jhb100-npu-syscon", "syscon"; + reg = <0x0 0x118e5000 0x0 0x100>; + }; + uart6: serial@11982000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x11982000 0x0 0x400>; @@ -413,7 +493,8 @@ uart6: serial@11982000 { per0crg: clock-controller@11a08000 { compatible = "starfive,jhb100-per0crg"; reg = <0x0 0x11a08000 0x0 0x1000>; - clocks = <&osc>, <&pll6>, + clocks = <&osc>, + <&per0pll JHB100_PER0PLL_PLL6_OUT>, <&sys0crg JHB100_SYS0CLK_BMCPER0_400>, <&sys0crg JHB100_SYS0CLK_BMCPER0_800>, <&sys0crg JHB100_SYS0CLK_BMCPER0_600>, @@ -425,10 +506,22 @@ per0crg: clock-controller@11a08000 { #reset-cells = <1>; }; + per0_syscon: syscon@11a09000 { + compatible = "starfive,jhb100-per0-syscon", "syscon", + "simple-mfd"; + reg = <0x0 0x11a09000 0x0 0x1000>; + + per0pll: clock-controller { + compatible = "starfive,jhb100-per0-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; + }; + per1crg: clock-controller@11b40000 { compatible = "starfive,jhb100-per1crg"; reg = <0x0 0x11b40000 0x0 0x1000>; - clocks = <&pll7>, + clocks = <&per1pll JHB100_PER1PLL_PLL7_OUT>, <&sys0crg JHB100_SYS0CLK_BMCPER1_600>, <&sys0crg JHB100_SYS0CLK_BMCPER1_800>, <&sys2crg JHB100_SYS2CLK_BMCPER1_200>, @@ -440,6 +533,18 @@ per1crg: clock-controller@11b40000 { #reset-cells = <1>; }; + per1_syscon: syscon@11b41000 { + compatible = "starfive,jhb100-per1-syscon", "syscon", + "simple-mfd"; + reg = <0x0 0x11b41000 0x0 0x1000>; + + per1pll: clock-controller { + compatible = "starfive,jhb100-per1-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; + }; + per2crg: clock-controller@11bc0000 { compatible = "starfive,jhb100-per2crg"; reg = <0x0 0x11bc0000 0x0 0x1000>; @@ -461,6 +566,11 @@ per2crg: clock-controller@11bc0000 { #reset-cells = <1>; }; + per2_syscon: syscon@11bc1000 { + compatible = "starfive,jhb100-per2-syscon", "syscon"; + reg = <0x0 0x11bc1000 0x0 0x1000>; + }; + per3crg: clock-controller@11c40000 { compatible = "starfive,jhb100-per3crg"; reg = <0x0 0x11c40000 0x0 0x1000>; @@ -480,11 +590,16 @@ per3crg: clock-controller@11c40000 { #reset-cells = <1>; }; + per3_syscon: syscon@11c41000 { + compatible = "starfive,jhb100-per3-syscon", "syscon"; + reg = <0x0 0x11c41000 0x0 0x1000>; + }; + sys0crg: clock-controller@13000000 { compatible = "starfive,jhb100-sys0crg"; reg = <0x0 0x13000000 0x0 0x4000>; clocks = <&osc>, <&pll0>, <&pll1>, - <&pll2>; + <&sys0pll JHB100_SYS0PLL_PLL2_OUT>; clock-names = "osc", "pll0", "pll1", "pll2"; #clock-cells = <1>; #reset-cells = <1>; @@ -494,7 +609,9 @@ sys1crg: clock-controller@13004000 { compatible = "starfive,jhb100-sys1crg"; reg = <0x0 0x13004000 0x0 0x4000>; clocks = <&osc>, <&pll0>, <&pll1>, - <&pll2>, <&pll4>, <&pll5>, + <&sys0pll JHB100_SYS0PLL_PLL2_OUT>, + <&sys0pll JHB100_SYS0PLL_PLL4_OUT>, + <&sys0pll JHB100_SYS0PLL_PLL5_OUT>, <&sys0crg JHB100_SYS0CLK_NPU_600>; clock-names = "osc", "pll0", "pll1", "pll2", "pll4", "pll5", "sys1_npu_600"; @@ -513,6 +630,41 @@ sys2crg: clock-controller@13008000 { #clock-cells = <1>; #reset-cells = <1>; }; + + sys0_syscon: syscon@13010000 { + compatible = "starfive,jhb100-sys0-syscon", "syscon", + "simple-mfd"; + reg = <0x0 0x13010000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x13010000 0x0 0x2000>; + + sys0pll: clock-controller { + compatible = "starfive,jhb100-sys0-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; + + chipid@38 { + compatible = "starfive,jhb100-socinfo"; + reg = <0x0 0x38 0x0 0x4>; + }; + }; + + sys1_syscon: syscon@13014000 { + compatible = "starfive,jhb100-sys1-syscon", "syscon"; + reg = <0x0 0x13014000 0x0 0x4000>; + }; + + sys2_syscon: syscon@13018000 { + compatible = "starfive,jhb100-sys2-syscon", "syscon"; + reg = <0x0 0x13018000 0x0 0x4000>; + }; + + strap_syscon: syscon@1301a000 { + compatible = "starfive,jhb100-strap-syscon", "syscon"; + reg = <0x0 0x1301a000 0x0 0x2000>; + }; }; }; }; -- 2.25.1