From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Alexey Charkov <alchark@gmail.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Keguang Zhang <keguang.zhang@gmail.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v1 01/13] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
Date: Thu, 2 Apr 2026 22:49:33 -0700 [thread overview]
Message-ID: <20260403054945.467700-2-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add documentation to describe StarFive JHB100 SoC System Controller
Registers.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../soc/starfive/starfive,jhb100-syscon.yaml | 140 ++++++++++++++++++
MAINTAINERS | 5 +
2 files changed, 145 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
new file mode 100644
index 000000000000..c0e1f6f68fa2
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 SoC system controller
+
+maintainers:
+ - Kevin Xie <kevin.xie@starfivetech.com>
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+description:
+ The StarFive JHB100 SoC system controller provides register information such
+ as offset, mask and shift to configure related modules such as PLL and PCIe.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - starfive,jhb100-pcierp-syscon
+ - starfive,jhb100-per0-syscon
+ - starfive,jhb100-per1-syscon
+ - starfive,jhb100-sys0-syscon
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - enum:
+ - starfive,jhb100-b2h-syscon
+ - starfive,jhb100-gpu-syscon
+ - starfive,jhb100-h2b-syscon
+ - starfive,jhb100-host-syscon
+ - starfive,jhb100-husb-syscon
+ - starfive,jhb100-husbcmn-syscon
+ - starfive,jhb100-husbd-syscon
+ - starfive,jhb100-npu-syscon
+ - starfive,jhb100-pcieep-ecsr-syscon
+ - starfive,jhb100-pcierp-ecsr-syscon
+ - starfive,jhb100-per2-syscon
+ - starfive,jhb100-per3-syscon
+ - starfive,jhb100-strap-syscon
+ - starfive,jhb100-sys1-syscon
+ - starfive,jhb100-sys2-syscon
+ - starfive,jhb100-usb-syscon
+ - starfive,jhb100-vout-syscon
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clock-controller:
+ $ref: /schemas/clock/starfive,jhb100-pll.yaml#
+ type: object
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jhb100-per0-syscon
+ - starfive,jhb100-per1-syscon
+ - starfive,jhb100-sys0-syscon
+ then:
+ required:
+ - clock-controller
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jhb100-sys0-syscon
+ then:
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ patternProperties:
+ "^chipid@[0-9a-f]+$":
+ $ref: /schemas/hwinfo/starfive,jhb100-socinfo.yaml#
+ type: object
+
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jhb100-pcierp-syscon
+ then:
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ patternProperties:
+ "^reset-controller@[0-9a-f]+$":
+ $ref: /schemas/reset/starfive,jhb100-reset-pcierp.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ syscon@10240000 {
+ compatible = "starfive,jhb100-b2h-syscon", "syscon";
+ reg = <0x0 0x10240000 0x0 0x1000>;
+ };
+
+ syscon@11719000 {
+ compatible = "starfive,jhb100-pcierp-syscon", "syscon",
+ "simple-mfd";
+ reg = <0x0 0x11719000 0x0 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x11719000 0x0 0x1000>;
+
+ reset-controller@14c {
+ compatible = "starfive,jhb100-reset-pcierp";
+ reg = <0x0 0x14c 0x0 0x4>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 4ddf8ba2e60d..eb5f6a383146 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25325,6 +25325,11 @@ S: Maintained
F: drivers/reset/starfive/reset-starfive-jhb1*
F: include/dt-bindings/reset/starfive,jhb1*.h
+STARFIVE JHB100 SYSCON
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
--
2.25.1
next prev parent reply other threads:[~2026-04-03 5:50 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-03 5:49 [PATCH v1 00/13] Add StarFive JHB100 syscon modules Changhuang Liang
2026-04-03 5:49 ` Changhuang Liang [this message]
2026-04-05 7:17 ` [PATCH v1 01/13] dt-bindings: soc: starfive: " Krzysztof Kozlowski
2026-04-03 5:49 ` [PATCH v1 02/13] dt-bindings: clock: Add system-0 domain PLL clock Changhuang Liang
2026-04-05 7:18 ` Krzysztof Kozlowski
2026-04-03 5:49 ` [PATCH v1 03/13] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-04-03 16:10 ` Brian Masney
2026-04-03 5:49 ` [PATCH v1 04/13] dt-bindings: clock: Add peripheral-0 domain PLL clock Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 05/13] clk: starfive: Add peripheral-0 domain PLL clock driver Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 06/13] dt-bindings: clock: Add peripheral-1 domain PLL clock Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 07/13] clk: starfive: Add Peripheral-1 domain PLL clock driver Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 08/13] dt-bindings: reset: Add StarFive JHB100 reset generator Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 09/13] reset: starfive: Introduce assert_polarity Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 10/13] reset: starfive: Add syscon reset driver support Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 11/13] dt-bindings: hwinfo: Add starfive,jhb100-socinfo Changhuang Liang
2026-04-05 7:19 ` Krzysztof Kozlowski
2026-04-03 5:49 ` [PATCH v1 12/13] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
2026-04-03 5:49 ` [PATCH v1 13/13] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
2026-04-05 7:18 ` [PATCH v1 00/13] Add StarFive JHB100 syscon modules Krzysztof Kozlowski
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