From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 795DF2750ED; Sun, 5 Apr 2026 15:28:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775402885; cv=none; b=W8yR1hSuArPw6bkYxsGtKxdenDkTvQoBGLlpMnK4F/hKnNiyILBPLfCeCfJ9dr3glQ7CpZOF4svysqJ96ECdyH4/jCQVf0AgTEZECdL9NjVGRthAR9OaIXknsMyiQhIKnYVGWFH1MmVXaoOX2SMFXiyPwe9L5MG1CN8shcJJTKw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775402885; c=relaxed/simple; bh=NDnBsbXnNGGHQG0turWSfj4CBg3TO2qRC78L3hPeXs4=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=f/G6aDiZLTTxAZsSRZOXDTw9Z1UHOf6jk8E58QljM7sagWUV4u6Ewlsrx7DUWU7pM54NGoBjG2Yr1A1+3wlsbGtP46p69JsTn+FXWHObhEUmiIaGRFd4IxIf0noxl8wTPVbUdWIMF3KxJJqa4jMpE4GRl/1R0S7R/ZdfCU/gGGY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=KvQWd+Gl; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="KvQWd+Gl" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 048E81BC0; Sun, 5 Apr 2026 08:27:49 -0700 (PDT) Received: from ryzen.lan (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E34383F62B; Sun, 5 Apr 2026 08:27:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775402874; bh=NDnBsbXnNGGHQG0turWSfj4CBg3TO2qRC78L3hPeXs4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=KvQWd+GlyQ26qJRkqKLtd0rZhhvYeTZuhURhP2De+TrJdzHLaXomuaxGKCg7V+Nmu Cq76diR6Q/0tGfEMAOK8ZxI5sR+DH/t5TeJTkhUA5i4JJEJ6ngsn8s9++hzFvakxNn hubn+aHBCVzSVgfa8MK94n19vR39SYApBGMpstuA= Date: Sun, 5 Apr 2026 17:27:38 +0200 From: Andre Przywara To: Chen-Yu Tsai Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/3] pinctrl: sunxi: a523: Remove unneeded IRQ remuxing flag Message-ID: <20260405172738.02530c80@ryzen.lan> In-Reply-To: References: <20260327113006.3135663-1-andre.przywara@arm.com> <20260327113006.3135663-2-andre.przywara@arm.com> Organization: Arm Ltd. X-Mailer: Claws Mail 4.2.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Fri, 27 Mar 2026 19:38:57 +0800 Chen-Yu Tsai wrote: Hi Linus, > On Fri, Mar 27, 2026 at 7:30=E2=80=AFPM Andre Przywara wrote: > > > > The Allwinner A10 and H3 SoCs cannot read the state of a GPIO line when > > that line is muxed for IRQ triggering (muxval 6), but only if it's > > explicitly muxed for GPIO input (muxval 0). Other SoCs do not show this > > behaviour, so we added a optional workaround, triggered by a quirk bit, > > which triggers remuxing the pin when it's configured for IRQ, while we > > need to read its value. > > > > For some reasons this quirk flag was copied over to newer SoCs, even > > though they don't show this behaviour, and the GPIO data register > > reflects the true GPIO state even with a pin muxed to IRQ trigger. > > > > Remove the unneeded quirk from the A523 family, where it's definitely > > not needed (confirmed by experiments), and where it actually breaks, > > because the workaround is not compatible with the newer generation > > pinctrl IP used in that chip. > > > > Together with a DT change this fixes GPIO IRQ operation on the A523 > > family of SoCs, as for instance used for the SD card detection. > > > > Signed-off-by: Andre Przywara > > Fixes: b8a51e95b376 ("pinctrl: sunxi: Add support for the secondary A52= 3 GPIO ports") =20 >=20 > Acked-by: Chen-Yu Tsai Can you possibly take this patch and maybe the binding (PATCH v2 2/3)? Ideally still for v7.0? IIUC Chen-Yu would take the DT patch, but relies on those two here. Thanks, Andre >=20 > > --- > > drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 1 - > > drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c | 1 - > > 2 files changed, 2 deletions(-) > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pi= nctrl/sunxi/pinctrl-sun55i-a523-r.c > > index 69cd2b4ebd7d..462aa1c4a5fa 100644 > > --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c > > @@ -26,7 +26,6 @@ static const u8 a523_r_irq_bank_muxes[SUNXI_PINCTRL_M= AX_BANKS] =3D > > static struct sunxi_pinctrl_desc a523_r_pinctrl_data =3D { > > .irq_banks =3D ARRAY_SIZE(a523_r_irq_bank_map), > > .irq_bank_map =3D a523_r_irq_bank_map, > > - .irq_read_needs_mux =3D true, > > .io_bias_cfg_variant =3D BIAS_VOLTAGE_PIO_POW_MODE_SEL, > > .pin_base =3D PL_BASE, > > }; > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinc= trl/sunxi/pinctrl-sun55i-a523.c > > index 7d2308c37d29..b6f78f1f30ac 100644 > > --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c > > @@ -26,7 +26,6 @@ static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX= _BANKS] =3D > > static struct sunxi_pinctrl_desc a523_pinctrl_data =3D { > > .irq_banks =3D ARRAY_SIZE(a523_irq_bank_map), > > .irq_bank_map =3D a523_irq_bank_map, > > - .irq_read_needs_mux =3D true, > > .io_bias_cfg_variant =3D BIAS_VOLTAGE_PIO_POW_MODE_SEL, > > }; > > > > -- > > 2.43.0 > > =20 >=20