* [PATCH 0/2] riscv: dts: sophgo: Fix CPU unit address for SG2042/SG2044 @ 2026-04-06 23:26 Inochi Amaoto 2026-04-06 23:26 ` [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address Inochi Amaoto 2026-04-06 23:26 ` [PATCH 2/2] riscv: dts: sophgo: sg2042: " Inochi Amaoto 0 siblings, 2 replies; 9+ messages in thread From: Inochi Amaoto @ 2026-04-06 23:26 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Inochi Amaoto, Han Gao, Nutty Liu, Guodong Xu, Guo Ren, Xiaoguang Xing Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan, Longbin Li The CPU unit addres for SG2042/SG2044 misused the decimal number for the unit address, Refer to this discussion in the Link, it should be in the hex format. Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/ Inochi Amaoto (2): riscv: dts: sophgo: sg2044: use hex for CPU unit address riscv: dts: sophgo: sg2042: use hex for CPU unit address arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++---------- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- 2 files changed, 236 insertions(+), 236 deletions(-) -- 2.53.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address 2026-04-06 23:26 [PATCH 0/2] riscv: dts: sophgo: Fix CPU unit address for SG2042/SG2044 Inochi Amaoto @ 2026-04-06 23:26 ` Inochi Amaoto 2026-04-07 1:26 ` Guo Ren 2026-04-06 23:26 ` [PATCH 2/2] riscv: dts: sophgo: sg2042: " Inochi Amaoto 1 sibling, 1 reply; 9+ messages in thread From: Inochi Amaoto @ 2026-04-06 23:26 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Inochi Amaoto, Han Gao, Nutty Liu, Guodong Xu, Guo Ren, Xiaoguang Xing Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan, Longbin Li Previous the CPU unit address cpu of sg2044 use decimal, it is not following the general convention for unit addresses of the OF. Convent the unit address to hex to resolve this problem. The introduces a small ABI break for the CPU id, but it should affect nothing since there is no direct full-path reference to these CPU nodes. Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/ --- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- 1 file changed, 118 insertions(+), 118 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi index 3135409c2149..f66a382c95bd 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi @@ -14,7 +14,7 @@ cpus { cpu0: cpu@0 { compatible = "thead,c920", "riscv"; - reg = <0>; + reg = <0x0>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { cpu1: cpu@1 { compatible = "thead,c920", "riscv"; - reg = <1>; + reg = <0x1>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { cpu2: cpu@2 { compatible = "thead,c920", "riscv"; - reg = <2>; + reg = <0x2>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { cpu3: cpu@3 { compatible = "thead,c920", "riscv"; - reg = <3>; + reg = <0x3>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { cpu4: cpu@4 { compatible = "thead,c920", "riscv"; - reg = <4>; + reg = <0x4>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { cpu5: cpu@5 { compatible = "thead,c920", "riscv"; - reg = <5>; + reg = <0x5>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { cpu6: cpu@6 { compatible = "thead,c920", "riscv"; - reg = <6>; + reg = <0x6>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { cpu7: cpu@7 { compatible = "thead,c920", "riscv"; - reg = <7>; + reg = <0x7>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { cpu8: cpu@8 { compatible = "thead,c920", "riscv"; - reg = <8>; + reg = <0x8>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { cpu9: cpu@9 { compatible = "thead,c920", "riscv"; - reg = <9>; + reg = <0x9>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { }; }; - cpu10: cpu@10 { + cpu10: cpu@a { compatible = "thead,c920", "riscv"; - reg = <10>; + reg = <0xa>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { }; }; - cpu11: cpu@11 { + cpu11: cpu@b { compatible = "thead,c920", "riscv"; - reg = <11>; + reg = <0xb>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { }; }; - cpu12: cpu@12 { + cpu12: cpu@c { compatible = "thead,c920", "riscv"; - reg = <12>; + reg = <0xc>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { }; }; - cpu13: cpu@13 { + cpu13: cpu@d { compatible = "thead,c920", "riscv"; - reg = <13>; + reg = <0xd>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { }; }; - cpu14: cpu@14 { + cpu14: cpu@e { compatible = "thead,c920", "riscv"; - reg = <14>; + reg = <0xe>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { }; }; - cpu15: cpu@15 { + cpu15: cpu@f { compatible = "thead,c920", "riscv"; - reg = <15>; + reg = <0xf>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { }; }; - cpu16: cpu@16 { + cpu16: cpu@10 { compatible = "thead,c920", "riscv"; - reg = <16>; + reg = <0x10>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { }; }; - cpu17: cpu@17 { + cpu17: cpu@11 { compatible = "thead,c920", "riscv"; - reg = <17>; + reg = <0x11>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { }; }; - cpu18: cpu@18 { + cpu18: cpu@12 { compatible = "thead,c920", "riscv"; - reg = <18>; + reg = <0x12>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { }; }; - cpu19: cpu@19 { + cpu19: cpu@13 { compatible = "thead,c920", "riscv"; - reg = <19>; + reg = <0x13>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { }; }; - cpu20: cpu@20 { + cpu20: cpu@14 { compatible = "thead,c920", "riscv"; - reg = <20>; + reg = <0x14>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { }; }; - cpu21: cpu@21 { + cpu21: cpu@15 { compatible = "thead,c920", "riscv"; - reg = <21>; + reg = <0x15>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { }; }; - cpu22: cpu@22 { + cpu22: cpu@16 { compatible = "thead,c920", "riscv"; - reg = <22>; + reg = <0x16>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { }; }; - cpu23: cpu@23 { + cpu23: cpu@17 { compatible = "thead,c920", "riscv"; - reg = <23>; + reg = <0x17>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { }; }; - cpu24: cpu@24 { + cpu24: cpu@18 { compatible = "thead,c920", "riscv"; - reg = <24>; + reg = <0x18>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { }; }; - cpu25: cpu@25 { + cpu25: cpu@19 { compatible = "thead,c920", "riscv"; - reg = <25>; + reg = <0x19>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { }; }; - cpu26: cpu@26 { + cpu26: cpu@1a { compatible = "thead,c920", "riscv"; - reg = <26>; + reg = <0x1a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { }; }; - cpu27: cpu@27 { + cpu27: cpu@1b { compatible = "thead,c920", "riscv"; - reg = <27>; + reg = <0x1b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { }; }; - cpu28: cpu@28 { + cpu28: cpu@1c { compatible = "thead,c920", "riscv"; - reg = <28>; + reg = <0x1c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { }; }; - cpu29: cpu@29 { + cpu29: cpu@1d { compatible = "thead,c920", "riscv"; - reg = <29>; + reg = <0x1d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { }; }; - cpu30: cpu@30 { + cpu30: cpu@1e { compatible = "thead,c920", "riscv"; - reg = <30>; + reg = <0x1e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { }; }; - cpu31: cpu@31 { + cpu31: cpu@1f { compatible = "thead,c920", "riscv"; - reg = <31>; + reg = <0x1f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { }; }; - cpu32: cpu@32 { + cpu32: cpu@20 { compatible = "thead,c920", "riscv"; - reg = <32>; + reg = <0x20>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { }; }; - cpu33: cpu@33 { + cpu33: cpu@21 { compatible = "thead,c920", "riscv"; - reg = <33>; + reg = <0x21>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { }; }; - cpu34: cpu@34 { + cpu34: cpu@22 { compatible = "thead,c920", "riscv"; - reg = <34>; + reg = <0x22>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { }; }; - cpu35: cpu@35 { + cpu35: cpu@23 { compatible = "thead,c920", "riscv"; - reg = <35>; + reg = <0x23>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { }; }; - cpu36: cpu@36 { + cpu36: cpu@24 { compatible = "thead,c920", "riscv"; - reg = <36>; + reg = <0x24>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { }; }; - cpu37: cpu@37 { + cpu37: cpu@25 { compatible = "thead,c920", "riscv"; - reg = <37>; + reg = <0x25>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { }; }; - cpu38: cpu@38 { + cpu38: cpu@26 { compatible = "thead,c920", "riscv"; - reg = <38>; + reg = <0x26>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { }; }; - cpu39: cpu@39 { + cpu39: cpu@27 { compatible = "thead,c920", "riscv"; - reg = <39>; + reg = <0x27>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { }; }; - cpu40: cpu@40 { + cpu40: cpu@28 { compatible = "thead,c920", "riscv"; - reg = <40>; + reg = <0x28>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { }; }; - cpu41: cpu@41 { + cpu41: cpu@29 { compatible = "thead,c920", "riscv"; - reg = <41>; + reg = <0x29>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { }; }; - cpu42: cpu@42 { + cpu42: cpu@2a { compatible = "thead,c920", "riscv"; - reg = <42>; + reg = <0x2a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { }; }; - cpu43: cpu@43 { + cpu43: cpu@2b { compatible = "thead,c920", "riscv"; - reg = <43>; + reg = <0x2b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { }; }; - cpu44: cpu@44 { + cpu44: cpu@2c { compatible = "thead,c920", "riscv"; - reg = <44>; + reg = <0x2c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { }; }; - cpu45: cpu@45 { + cpu45: cpu@2d { compatible = "thead,c920", "riscv"; - reg = <45>; + reg = <0x2d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { }; }; - cpu46: cpu@46 { + cpu46: cpu@2e { compatible = "thead,c920", "riscv"; - reg = <46>; + reg = <0x2e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { }; }; - cpu47: cpu@47 { + cpu47: cpu@2f { compatible = "thead,c920", "riscv"; - reg = <47>; + reg = <0x2f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { }; }; - cpu48: cpu@48 { + cpu48: cpu@30 { compatible = "thead,c920", "riscv"; - reg = <48>; + reg = <0x30>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { }; }; - cpu49: cpu@49 { + cpu49: cpu@31 { compatible = "thead,c920", "riscv"; - reg = <49>; + reg = <0x31>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { }; }; - cpu50: cpu@50 { + cpu50: cpu@32 { compatible = "thead,c920", "riscv"; - reg = <50>; + reg = <0x32>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { }; }; - cpu51: cpu@51 { + cpu51: cpu@33 { compatible = "thead,c920", "riscv"; - reg = <51>; + reg = <0x33>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { }; }; - cpu52: cpu@52 { + cpu52: cpu@34 { compatible = "thead,c920", "riscv"; - reg = <52>; + reg = <0x34>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { }; }; - cpu53: cpu@53 { + cpu53: cpu@35 { compatible = "thead,c920", "riscv"; - reg = <53>; + reg = <0x35>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { }; }; - cpu54: cpu@54 { + cpu54: cpu@36 { compatible = "thead,c920", "riscv"; - reg = <54>; + reg = <0x36>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { }; }; - cpu55: cpu@55 { + cpu55: cpu@37 { compatible = "thead,c920", "riscv"; - reg = <55>; + reg = <0x37>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { }; }; - cpu56: cpu@56 { + cpu56: cpu@38 { compatible = "thead,c920", "riscv"; - reg = <56>; + reg = <0x38>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { }; }; - cpu57: cpu@57 { + cpu57: cpu@39 { compatible = "thead,c920", "riscv"; - reg = <57>; + reg = <0x39>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { }; }; - cpu58: cpu@58 { + cpu58: cpu@3a { compatible = "thead,c920", "riscv"; - reg = <58>; + reg = <0x3a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { }; }; - cpu59: cpu@59 { + cpu59: cpu@3b { compatible = "thead,c920", "riscv"; - reg = <59>; + reg = <0x3b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { }; }; - cpu60: cpu@60 { + cpu60: cpu@3c { compatible = "thead,c920", "riscv"; - reg = <60>; + reg = <0x3c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { }; }; - cpu61: cpu@61 { + cpu61: cpu@3d { compatible = "thead,c920", "riscv"; - reg = <61>; + reg = <0x3d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { }; }; - cpu62: cpu@62 { + cpu62: cpu@3e { compatible = "thead,c920", "riscv"; - reg = <62>; + reg = <0x3e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { }; }; - cpu63: cpu@63 { + cpu63: cpu@3f { compatible = "thead,c920", "riscv"; - reg = <63>; + reg = <0x3f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; -- 2.53.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address 2026-04-06 23:26 ` [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address Inochi Amaoto @ 2026-04-07 1:26 ` Guo Ren 2026-04-07 2:36 ` Inochi Amaoto 0 siblings, 1 reply; 9+ messages in thread From: Guo Ren @ 2026-04-07 1:26 UTC (permalink / raw) To: Inochi Amaoto Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Han Gao, Nutty Liu, Guodong Xu, Xiaoguang Xing, devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan, Longbin Li On Tue, Apr 7, 2026 at 7:27 AM Inochi Amaoto <inochiama@gmail.com> wrote: > > Previous the CPU unit address cpu of sg2044 use decimal, it is > not following the general convention for unit addresses of the > OF. Convent the unit address to hex to resolve this problem. > > The introduces a small ABI break for the CPU id, but it should > affect nothing since there is no direct full-path reference to > these CPU nodes. > > Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/ Remove the Link tag, and add: Reviewed-by: Guo Ren <guoren@kernel.org> > --- > arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- > 1 file changed, 118 insertions(+), 118 deletions(-) > > diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > index 3135409c2149..f66a382c95bd 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > @@ -14,7 +14,7 @@ cpus { > > cpu0: cpu@0 { > compatible = "thead,c920", "riscv"; > - reg = <0>; > + reg = <0x0>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { > > cpu1: cpu@1 { > compatible = "thead,c920", "riscv"; > - reg = <1>; > + reg = <0x1>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { > > cpu2: cpu@2 { > compatible = "thead,c920", "riscv"; > - reg = <2>; > + reg = <0x2>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { > > cpu3: cpu@3 { > compatible = "thead,c920", "riscv"; > - reg = <3>; > + reg = <0x3>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { > > cpu4: cpu@4 { > compatible = "thead,c920", "riscv"; > - reg = <4>; > + reg = <0x4>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { > > cpu5: cpu@5 { > compatible = "thead,c920", "riscv"; > - reg = <5>; > + reg = <0x5>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { > > cpu6: cpu@6 { > compatible = "thead,c920", "riscv"; > - reg = <6>; > + reg = <0x6>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { > > cpu7: cpu@7 { > compatible = "thead,c920", "riscv"; > - reg = <7>; > + reg = <0x7>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { > > cpu8: cpu@8 { > compatible = "thead,c920", "riscv"; > - reg = <8>; > + reg = <0x8>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { > > cpu9: cpu@9 { > compatible = "thead,c920", "riscv"; > - reg = <9>; > + reg = <0x9>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { > }; > }; > > - cpu10: cpu@10 { > + cpu10: cpu@a { > compatible = "thead,c920", "riscv"; > - reg = <10>; > + reg = <0xa>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { > }; > }; > > - cpu11: cpu@11 { > + cpu11: cpu@b { > compatible = "thead,c920", "riscv"; > - reg = <11>; > + reg = <0xb>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { > }; > }; > > - cpu12: cpu@12 { > + cpu12: cpu@c { > compatible = "thead,c920", "riscv"; > - reg = <12>; > + reg = <0xc>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { > }; > }; > > - cpu13: cpu@13 { > + cpu13: cpu@d { > compatible = "thead,c920", "riscv"; > - reg = <13>; > + reg = <0xd>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { > }; > }; > > - cpu14: cpu@14 { > + cpu14: cpu@e { > compatible = "thead,c920", "riscv"; > - reg = <14>; > + reg = <0xe>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { > }; > }; > > - cpu15: cpu@15 { > + cpu15: cpu@f { > compatible = "thead,c920", "riscv"; > - reg = <15>; > + reg = <0xf>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { > }; > }; > > - cpu16: cpu@16 { > + cpu16: cpu@10 { > compatible = "thead,c920", "riscv"; > - reg = <16>; > + reg = <0x10>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { > }; > }; > > - cpu17: cpu@17 { > + cpu17: cpu@11 { > compatible = "thead,c920", "riscv"; > - reg = <17>; > + reg = <0x11>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { > }; > }; > > - cpu18: cpu@18 { > + cpu18: cpu@12 { > compatible = "thead,c920", "riscv"; > - reg = <18>; > + reg = <0x12>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { > }; > }; > > - cpu19: cpu@19 { > + cpu19: cpu@13 { > compatible = "thead,c920", "riscv"; > - reg = <19>; > + reg = <0x13>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { > }; > }; > > - cpu20: cpu@20 { > + cpu20: cpu@14 { > compatible = "thead,c920", "riscv"; > - reg = <20>; > + reg = <0x14>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { > }; > }; > > - cpu21: cpu@21 { > + cpu21: cpu@15 { > compatible = "thead,c920", "riscv"; > - reg = <21>; > + reg = <0x15>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { > }; > }; > > - cpu22: cpu@22 { > + cpu22: cpu@16 { > compatible = "thead,c920", "riscv"; > - reg = <22>; > + reg = <0x16>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { > }; > }; > > - cpu23: cpu@23 { > + cpu23: cpu@17 { > compatible = "thead,c920", "riscv"; > - reg = <23>; > + reg = <0x17>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { > }; > }; > > - cpu24: cpu@24 { > + cpu24: cpu@18 { > compatible = "thead,c920", "riscv"; > - reg = <24>; > + reg = <0x18>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { > }; > }; > > - cpu25: cpu@25 { > + cpu25: cpu@19 { > compatible = "thead,c920", "riscv"; > - reg = <25>; > + reg = <0x19>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { > }; > }; > > - cpu26: cpu@26 { > + cpu26: cpu@1a { > compatible = "thead,c920", "riscv"; > - reg = <26>; > + reg = <0x1a>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { > }; > }; > > - cpu27: cpu@27 { > + cpu27: cpu@1b { > compatible = "thead,c920", "riscv"; > - reg = <27>; > + reg = <0x1b>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { > }; > }; > > - cpu28: cpu@28 { > + cpu28: cpu@1c { > compatible = "thead,c920", "riscv"; > - reg = <28>; > + reg = <0x1c>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { > }; > }; > > - cpu29: cpu@29 { > + cpu29: cpu@1d { > compatible = "thead,c920", "riscv"; > - reg = <29>; > + reg = <0x1d>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { > }; > }; > > - cpu30: cpu@30 { > + cpu30: cpu@1e { > compatible = "thead,c920", "riscv"; > - reg = <30>; > + reg = <0x1e>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { > }; > }; > > - cpu31: cpu@31 { > + cpu31: cpu@1f { > compatible = "thead,c920", "riscv"; > - reg = <31>; > + reg = <0x1f>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { > }; > }; > > - cpu32: cpu@32 { > + cpu32: cpu@20 { > compatible = "thead,c920", "riscv"; > - reg = <32>; > + reg = <0x20>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { > }; > }; > > - cpu33: cpu@33 { > + cpu33: cpu@21 { > compatible = "thead,c920", "riscv"; > - reg = <33>; > + reg = <0x21>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { > }; > }; > > - cpu34: cpu@34 { > + cpu34: cpu@22 { > compatible = "thead,c920", "riscv"; > - reg = <34>; > + reg = <0x22>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { > }; > }; > > - cpu35: cpu@35 { > + cpu35: cpu@23 { > compatible = "thead,c920", "riscv"; > - reg = <35>; > + reg = <0x23>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { > }; > }; > > - cpu36: cpu@36 { > + cpu36: cpu@24 { > compatible = "thead,c920", "riscv"; > - reg = <36>; > + reg = <0x24>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { > }; > }; > > - cpu37: cpu@37 { > + cpu37: cpu@25 { > compatible = "thead,c920", "riscv"; > - reg = <37>; > + reg = <0x25>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { > }; > }; > > - cpu38: cpu@38 { > + cpu38: cpu@26 { > compatible = "thead,c920", "riscv"; > - reg = <38>; > + reg = <0x26>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { > }; > }; > > - cpu39: cpu@39 { > + cpu39: cpu@27 { > compatible = "thead,c920", "riscv"; > - reg = <39>; > + reg = <0x27>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { > }; > }; > > - cpu40: cpu@40 { > + cpu40: cpu@28 { > compatible = "thead,c920", "riscv"; > - reg = <40>; > + reg = <0x28>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { > }; > }; > > - cpu41: cpu@41 { > + cpu41: cpu@29 { > compatible = "thead,c920", "riscv"; > - reg = <41>; > + reg = <0x29>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { > }; > }; > > - cpu42: cpu@42 { > + cpu42: cpu@2a { > compatible = "thead,c920", "riscv"; > - reg = <42>; > + reg = <0x2a>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { > }; > }; > > - cpu43: cpu@43 { > + cpu43: cpu@2b { > compatible = "thead,c920", "riscv"; > - reg = <43>; > + reg = <0x2b>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { > }; > }; > > - cpu44: cpu@44 { > + cpu44: cpu@2c { > compatible = "thead,c920", "riscv"; > - reg = <44>; > + reg = <0x2c>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { > }; > }; > > - cpu45: cpu@45 { > + cpu45: cpu@2d { > compatible = "thead,c920", "riscv"; > - reg = <45>; > + reg = <0x2d>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { > }; > }; > > - cpu46: cpu@46 { > + cpu46: cpu@2e { > compatible = "thead,c920", "riscv"; > - reg = <46>; > + reg = <0x2e>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { > }; > }; > > - cpu47: cpu@47 { > + cpu47: cpu@2f { > compatible = "thead,c920", "riscv"; > - reg = <47>; > + reg = <0x2f>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { > }; > }; > > - cpu48: cpu@48 { > + cpu48: cpu@30 { > compatible = "thead,c920", "riscv"; > - reg = <48>; > + reg = <0x30>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { > }; > }; > > - cpu49: cpu@49 { > + cpu49: cpu@31 { > compatible = "thead,c920", "riscv"; > - reg = <49>; > + reg = <0x31>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { > }; > }; > > - cpu50: cpu@50 { > + cpu50: cpu@32 { > compatible = "thead,c920", "riscv"; > - reg = <50>; > + reg = <0x32>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { > }; > }; > > - cpu51: cpu@51 { > + cpu51: cpu@33 { > compatible = "thead,c920", "riscv"; > - reg = <51>; > + reg = <0x33>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { > }; > }; > > - cpu52: cpu@52 { > + cpu52: cpu@34 { > compatible = "thead,c920", "riscv"; > - reg = <52>; > + reg = <0x34>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { > }; > }; > > - cpu53: cpu@53 { > + cpu53: cpu@35 { > compatible = "thead,c920", "riscv"; > - reg = <53>; > + reg = <0x35>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { > }; > }; > > - cpu54: cpu@54 { > + cpu54: cpu@36 { > compatible = "thead,c920", "riscv"; > - reg = <54>; > + reg = <0x36>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { > }; > }; > > - cpu55: cpu@55 { > + cpu55: cpu@37 { > compatible = "thead,c920", "riscv"; > - reg = <55>; > + reg = <0x37>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { > }; > }; > > - cpu56: cpu@56 { > + cpu56: cpu@38 { > compatible = "thead,c920", "riscv"; > - reg = <56>; > + reg = <0x38>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { > }; > }; > > - cpu57: cpu@57 { > + cpu57: cpu@39 { > compatible = "thead,c920", "riscv"; > - reg = <57>; > + reg = <0x39>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { > }; > }; > > - cpu58: cpu@58 { > + cpu58: cpu@3a { > compatible = "thead,c920", "riscv"; > - reg = <58>; > + reg = <0x3a>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { > }; > }; > > - cpu59: cpu@59 { > + cpu59: cpu@3b { > compatible = "thead,c920", "riscv"; > - reg = <59>; > + reg = <0x3b>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { > }; > }; > > - cpu60: cpu@60 { > + cpu60: cpu@3c { > compatible = "thead,c920", "riscv"; > - reg = <60>; > + reg = <0x3c>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { > }; > }; > > - cpu61: cpu@61 { > + cpu61: cpu@3d { > compatible = "thead,c920", "riscv"; > - reg = <61>; > + reg = <0x3d>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { > }; > }; > > - cpu62: cpu@62 { > + cpu62: cpu@3e { > compatible = "thead,c920", "riscv"; > - reg = <62>; > + reg = <0x3e>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { > }; > }; > > - cpu63: cpu@63 { > + cpu63: cpu@3f { > compatible = "thead,c920", "riscv"; > - reg = <63>; > + reg = <0x3f>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > -- > 2.53.0 > -- Best Regards Guo Ren ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address 2026-04-07 1:26 ` Guo Ren @ 2026-04-07 2:36 ` Inochi Amaoto 2026-04-07 3:08 ` Guo Ren 0 siblings, 1 reply; 9+ messages in thread From: Inochi Amaoto @ 2026-04-07 2:36 UTC (permalink / raw) To: Guo Ren, Inochi Amaoto Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Han Gao, Nutty Liu, Guodong Xu, Xiaoguang Xing, devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan, Longbin Li On Tue, Apr 07, 2026 at 09:26:11AM +0800, Guo Ren wrote: > On Tue, Apr 7, 2026 at 7:27 AM Inochi Amaoto <inochiama@gmail.com> wrote: > > > > Previous the CPU unit address cpu of sg2044 use decimal, it is > > not following the general convention for unit addresses of the > > OF. Convent the unit address to hex to resolve this problem. > > > > The introduces a small ABI break for the CPU id, but it should > > affect nothing since there is no direct full-path reference to > > these CPU nodes. > > > > Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > > Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/ > > Remove the Link tag, and add: > > Reviewed-by: Guo Ren <guoren@kernel.org> > This link provides the motivation for this patch, I think it will be fine for other to know why this patch is needed. Regards, Inochi > > --- > > arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- > > 1 file changed, 118 insertions(+), 118 deletions(-) > > > > diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > > index 3135409c2149..f66a382c95bd 100644 > > --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > > @@ -14,7 +14,7 @@ cpus { > > > > cpu0: cpu@0 { > > compatible = "thead,c920", "riscv"; > > - reg = <0>; > > + reg = <0x0>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { > > > > cpu1: cpu@1 { > > compatible = "thead,c920", "riscv"; > > - reg = <1>; > > + reg = <0x1>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { > > > > cpu2: cpu@2 { > > compatible = "thead,c920", "riscv"; > > - reg = <2>; > > + reg = <0x2>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { > > > > cpu3: cpu@3 { > > compatible = "thead,c920", "riscv"; > > - reg = <3>; > > + reg = <0x3>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { > > > > cpu4: cpu@4 { > > compatible = "thead,c920", "riscv"; > > - reg = <4>; > > + reg = <0x4>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { > > > > cpu5: cpu@5 { > > compatible = "thead,c920", "riscv"; > > - reg = <5>; > > + reg = <0x5>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { > > > > cpu6: cpu@6 { > > compatible = "thead,c920", "riscv"; > > - reg = <6>; > > + reg = <0x6>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { > > > > cpu7: cpu@7 { > > compatible = "thead,c920", "riscv"; > > - reg = <7>; > > + reg = <0x7>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { > > > > cpu8: cpu@8 { > > compatible = "thead,c920", "riscv"; > > - reg = <8>; > > + reg = <0x8>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { > > > > cpu9: cpu@9 { > > compatible = "thead,c920", "riscv"; > > - reg = <9>; > > + reg = <0x9>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { > > }; > > }; > > > > - cpu10: cpu@10 { > > + cpu10: cpu@a { > > compatible = "thead,c920", "riscv"; > > - reg = <10>; > > + reg = <0xa>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { > > }; > > }; > > > > - cpu11: cpu@11 { > > + cpu11: cpu@b { > > compatible = "thead,c920", "riscv"; > > - reg = <11>; > > + reg = <0xb>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { > > }; > > }; > > > > - cpu12: cpu@12 { > > + cpu12: cpu@c { > > compatible = "thead,c920", "riscv"; > > - reg = <12>; > > + reg = <0xc>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { > > }; > > }; > > > > - cpu13: cpu@13 { > > + cpu13: cpu@d { > > compatible = "thead,c920", "riscv"; > > - reg = <13>; > > + reg = <0xd>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { > > }; > > }; > > > > - cpu14: cpu@14 { > > + cpu14: cpu@e { > > compatible = "thead,c920", "riscv"; > > - reg = <14>; > > + reg = <0xe>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { > > }; > > }; > > > > - cpu15: cpu@15 { > > + cpu15: cpu@f { > > compatible = "thead,c920", "riscv"; > > - reg = <15>; > > + reg = <0xf>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { > > }; > > }; > > > > - cpu16: cpu@16 { > > + cpu16: cpu@10 { > > compatible = "thead,c920", "riscv"; > > - reg = <16>; > > + reg = <0x10>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { > > }; > > }; > > > > - cpu17: cpu@17 { > > + cpu17: cpu@11 { > > compatible = "thead,c920", "riscv"; > > - reg = <17>; > > + reg = <0x11>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { > > }; > > }; > > > > - cpu18: cpu@18 { > > + cpu18: cpu@12 { > > compatible = "thead,c920", "riscv"; > > - reg = <18>; > > + reg = <0x12>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { > > }; > > }; > > > > - cpu19: cpu@19 { > > + cpu19: cpu@13 { > > compatible = "thead,c920", "riscv"; > > - reg = <19>; > > + reg = <0x13>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { > > }; > > }; > > > > - cpu20: cpu@20 { > > + cpu20: cpu@14 { > > compatible = "thead,c920", "riscv"; > > - reg = <20>; > > + reg = <0x14>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { > > }; > > }; > > > > - cpu21: cpu@21 { > > + cpu21: cpu@15 { > > compatible = "thead,c920", "riscv"; > > - reg = <21>; > > + reg = <0x15>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { > > }; > > }; > > > > - cpu22: cpu@22 { > > + cpu22: cpu@16 { > > compatible = "thead,c920", "riscv"; > > - reg = <22>; > > + reg = <0x16>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { > > }; > > }; > > > > - cpu23: cpu@23 { > > + cpu23: cpu@17 { > > compatible = "thead,c920", "riscv"; > > - reg = <23>; > > + reg = <0x17>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { > > }; > > }; > > > > - cpu24: cpu@24 { > > + cpu24: cpu@18 { > > compatible = "thead,c920", "riscv"; > > - reg = <24>; > > + reg = <0x18>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { > > }; > > }; > > > > - cpu25: cpu@25 { > > + cpu25: cpu@19 { > > compatible = "thead,c920", "riscv"; > > - reg = <25>; > > + reg = <0x19>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { > > }; > > }; > > > > - cpu26: cpu@26 { > > + cpu26: cpu@1a { > > compatible = "thead,c920", "riscv"; > > - reg = <26>; > > + reg = <0x1a>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { > > }; > > }; > > > > - cpu27: cpu@27 { > > + cpu27: cpu@1b { > > compatible = "thead,c920", "riscv"; > > - reg = <27>; > > + reg = <0x1b>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { > > }; > > }; > > > > - cpu28: cpu@28 { > > + cpu28: cpu@1c { > > compatible = "thead,c920", "riscv"; > > - reg = <28>; > > + reg = <0x1c>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { > > }; > > }; > > > > - cpu29: cpu@29 { > > + cpu29: cpu@1d { > > compatible = "thead,c920", "riscv"; > > - reg = <29>; > > + reg = <0x1d>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { > > }; > > }; > > > > - cpu30: cpu@30 { > > + cpu30: cpu@1e { > > compatible = "thead,c920", "riscv"; > > - reg = <30>; > > + reg = <0x1e>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { > > }; > > }; > > > > - cpu31: cpu@31 { > > + cpu31: cpu@1f { > > compatible = "thead,c920", "riscv"; > > - reg = <31>; > > + reg = <0x1f>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { > > }; > > }; > > > > - cpu32: cpu@32 { > > + cpu32: cpu@20 { > > compatible = "thead,c920", "riscv"; > > - reg = <32>; > > + reg = <0x20>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { > > }; > > }; > > > > - cpu33: cpu@33 { > > + cpu33: cpu@21 { > > compatible = "thead,c920", "riscv"; > > - reg = <33>; > > + reg = <0x21>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { > > }; > > }; > > > > - cpu34: cpu@34 { > > + cpu34: cpu@22 { > > compatible = "thead,c920", "riscv"; > > - reg = <34>; > > + reg = <0x22>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { > > }; > > }; > > > > - cpu35: cpu@35 { > > + cpu35: cpu@23 { > > compatible = "thead,c920", "riscv"; > > - reg = <35>; > > + reg = <0x23>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { > > }; > > }; > > > > - cpu36: cpu@36 { > > + cpu36: cpu@24 { > > compatible = "thead,c920", "riscv"; > > - reg = <36>; > > + reg = <0x24>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { > > }; > > }; > > > > - cpu37: cpu@37 { > > + cpu37: cpu@25 { > > compatible = "thead,c920", "riscv"; > > - reg = <37>; > > + reg = <0x25>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { > > }; > > }; > > > > - cpu38: cpu@38 { > > + cpu38: cpu@26 { > > compatible = "thead,c920", "riscv"; > > - reg = <38>; > > + reg = <0x26>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { > > }; > > }; > > > > - cpu39: cpu@39 { > > + cpu39: cpu@27 { > > compatible = "thead,c920", "riscv"; > > - reg = <39>; > > + reg = <0x27>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { > > }; > > }; > > > > - cpu40: cpu@40 { > > + cpu40: cpu@28 { > > compatible = "thead,c920", "riscv"; > > - reg = <40>; > > + reg = <0x28>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { > > }; > > }; > > > > - cpu41: cpu@41 { > > + cpu41: cpu@29 { > > compatible = "thead,c920", "riscv"; > > - reg = <41>; > > + reg = <0x29>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { > > }; > > }; > > > > - cpu42: cpu@42 { > > + cpu42: cpu@2a { > > compatible = "thead,c920", "riscv"; > > - reg = <42>; > > + reg = <0x2a>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { > > }; > > }; > > > > - cpu43: cpu@43 { > > + cpu43: cpu@2b { > > compatible = "thead,c920", "riscv"; > > - reg = <43>; > > + reg = <0x2b>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { > > }; > > }; > > > > - cpu44: cpu@44 { > > + cpu44: cpu@2c { > > compatible = "thead,c920", "riscv"; > > - reg = <44>; > > + reg = <0x2c>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { > > }; > > }; > > > > - cpu45: cpu@45 { > > + cpu45: cpu@2d { > > compatible = "thead,c920", "riscv"; > > - reg = <45>; > > + reg = <0x2d>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { > > }; > > }; > > > > - cpu46: cpu@46 { > > + cpu46: cpu@2e { > > compatible = "thead,c920", "riscv"; > > - reg = <46>; > > + reg = <0x2e>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { > > }; > > }; > > > > - cpu47: cpu@47 { > > + cpu47: cpu@2f { > > compatible = "thead,c920", "riscv"; > > - reg = <47>; > > + reg = <0x2f>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { > > }; > > }; > > > > - cpu48: cpu@48 { > > + cpu48: cpu@30 { > > compatible = "thead,c920", "riscv"; > > - reg = <48>; > > + reg = <0x30>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { > > }; > > }; > > > > - cpu49: cpu@49 { > > + cpu49: cpu@31 { > > compatible = "thead,c920", "riscv"; > > - reg = <49>; > > + reg = <0x31>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { > > }; > > }; > > > > - cpu50: cpu@50 { > > + cpu50: cpu@32 { > > compatible = "thead,c920", "riscv"; > > - reg = <50>; > > + reg = <0x32>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { > > }; > > }; > > > > - cpu51: cpu@51 { > > + cpu51: cpu@33 { > > compatible = "thead,c920", "riscv"; > > - reg = <51>; > > + reg = <0x33>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { > > }; > > }; > > > > - cpu52: cpu@52 { > > + cpu52: cpu@34 { > > compatible = "thead,c920", "riscv"; > > - reg = <52>; > > + reg = <0x34>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { > > }; > > }; > > > > - cpu53: cpu@53 { > > + cpu53: cpu@35 { > > compatible = "thead,c920", "riscv"; > > - reg = <53>; > > + reg = <0x35>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { > > }; > > }; > > > > - cpu54: cpu@54 { > > + cpu54: cpu@36 { > > compatible = "thead,c920", "riscv"; > > - reg = <54>; > > + reg = <0x36>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { > > }; > > }; > > > > - cpu55: cpu@55 { > > + cpu55: cpu@37 { > > compatible = "thead,c920", "riscv"; > > - reg = <55>; > > + reg = <0x37>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { > > }; > > }; > > > > - cpu56: cpu@56 { > > + cpu56: cpu@38 { > > compatible = "thead,c920", "riscv"; > > - reg = <56>; > > + reg = <0x38>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { > > }; > > }; > > > > - cpu57: cpu@57 { > > + cpu57: cpu@39 { > > compatible = "thead,c920", "riscv"; > > - reg = <57>; > > + reg = <0x39>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { > > }; > > }; > > > > - cpu58: cpu@58 { > > + cpu58: cpu@3a { > > compatible = "thead,c920", "riscv"; > > - reg = <58>; > > + reg = <0x3a>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { > > }; > > }; > > > > - cpu59: cpu@59 { > > + cpu59: cpu@3b { > > compatible = "thead,c920", "riscv"; > > - reg = <59>; > > + reg = <0x3b>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { > > }; > > }; > > > > - cpu60: cpu@60 { > > + cpu60: cpu@3c { > > compatible = "thead,c920", "riscv"; > > - reg = <60>; > > + reg = <0x3c>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { > > }; > > }; > > > > - cpu61: cpu@61 { > > + cpu61: cpu@3d { > > compatible = "thead,c920", "riscv"; > > - reg = <61>; > > + reg = <0x3d>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { > > }; > > }; > > > > - cpu62: cpu@62 { > > + cpu62: cpu@3e { > > compatible = "thead,c920", "riscv"; > > - reg = <62>; > > + reg = <0x3e>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > @@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { > > }; > > }; > > > > - cpu63: cpu@63 { > > + cpu63: cpu@3f { > > compatible = "thead,c920", "riscv"; > > - reg = <63>; > > + reg = <0x3f>; > > i-cache-block-size = <64>; > > i-cache-size = <65536>; > > i-cache-sets = <512>; > > -- > > 2.53.0 > > > > > -- > Best Regards > Guo Ren ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address 2026-04-07 2:36 ` Inochi Amaoto @ 2026-04-07 3:08 ` Guo Ren 2026-04-07 3:35 ` Inochi Amaoto 0 siblings, 1 reply; 9+ messages in thread From: Guo Ren @ 2026-04-07 3:08 UTC (permalink / raw) To: Inochi Amaoto Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Han Gao, Nutty Liu, Guodong Xu, Xiaoguang Xing, devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan, Longbin Li On Tue, Apr 7, 2026 at 10:37 AM Inochi Amaoto <inochiama@gmail.com> wrote: > > On Tue, Apr 07, 2026 at 09:26:11AM +0800, Guo Ren wrote: > > On Tue, Apr 7, 2026 at 7:27 AM Inochi Amaoto <inochiama@gmail.com> wrote: > > > > > > Previous the CPU unit address cpu of sg2044 use decimal, it is > > > not following the general convention for unit addresses of the > > > OF. Convent the unit address to hex to resolve this problem. > > > > > > The introduces a small ABI break for the CPU id, but it should > > > affect nothing since there is no direct full-path reference to > > > these CPU nodes. > > > > > > Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") > > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > > > Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/ > > > > Remove the Link tag, and add: > > > > Reviewed-by: Guo Ren <guoren@kernel.org> > > > > This link provides the motivation for this patch, I think it will be > fine for other to know why this patch is needed. The commit log already clearly describes the motivation: - why we need to change from decimal to hex (OF unit address convention), - the small ABI impact, - and the Fixes tag. Adding a Link: tag that points back to the discussion thread doesn't provide any additional information beyond what's already in the commit message. In my opinion, the commit log is sufficient and self-contained. Linus recently made it very clear that he wants us to stop adding these kinds of low-value Link tags, as they just waste reviewers' time: https://www.phoronix.com/news/Linus-Torvalds-No-Link-Tags > > Regards, > Inochi > > > > --- > > > arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- > > > 1 file changed, 118 insertions(+), 118 deletions(-) > > > > > > diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > > > index 3135409c2149..f66a382c95bd 100644 > > > --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > > > +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > > > @@ -14,7 +14,7 @@ cpus { > > > > > > cpu0: cpu@0 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <0>; > > > + reg = <0x0>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { > > > > > > cpu1: cpu@1 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <1>; > > > + reg = <0x1>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { > > > > > > cpu2: cpu@2 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <2>; > > > + reg = <0x2>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { > > > > > > cpu3: cpu@3 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <3>; > > > + reg = <0x3>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { > > > > > > cpu4: cpu@4 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <4>; > > > + reg = <0x4>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { > > > > > > cpu5: cpu@5 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <5>; > > > + reg = <0x5>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { > > > > > > cpu6: cpu@6 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <6>; > > > + reg = <0x6>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { > > > > > > cpu7: cpu@7 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <7>; > > > + reg = <0x7>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { > > > > > > cpu8: cpu@8 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <8>; > > > + reg = <0x8>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { > > > > > > cpu9: cpu@9 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <9>; > > > + reg = <0x9>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu10: cpu@10 { > > > + cpu10: cpu@a { > > > compatible = "thead,c920", "riscv"; > > > - reg = <10>; > > > + reg = <0xa>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu11: cpu@11 { > > > + cpu11: cpu@b { > > > compatible = "thead,c920", "riscv"; > > > - reg = <11>; > > > + reg = <0xb>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu12: cpu@12 { > > > + cpu12: cpu@c { > > > compatible = "thead,c920", "riscv"; > > > - reg = <12>; > > > + reg = <0xc>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu13: cpu@13 { > > > + cpu13: cpu@d { > > > compatible = "thead,c920", "riscv"; > > > - reg = <13>; > > > + reg = <0xd>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu14: cpu@14 { > > > + cpu14: cpu@e { > > > compatible = "thead,c920", "riscv"; > > > - reg = <14>; > > > + reg = <0xe>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu15: cpu@15 { > > > + cpu15: cpu@f { > > > compatible = "thead,c920", "riscv"; > > > - reg = <15>; > > > + reg = <0xf>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu16: cpu@16 { > > > + cpu16: cpu@10 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <16>; > > > + reg = <0x10>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu17: cpu@17 { > > > + cpu17: cpu@11 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <17>; > > > + reg = <0x11>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu18: cpu@18 { > > > + cpu18: cpu@12 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <18>; > > > + reg = <0x12>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu19: cpu@19 { > > > + cpu19: cpu@13 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <19>; > > > + reg = <0x13>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu20: cpu@20 { > > > + cpu20: cpu@14 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <20>; > > > + reg = <0x14>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu21: cpu@21 { > > > + cpu21: cpu@15 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <21>; > > > + reg = <0x15>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu22: cpu@22 { > > > + cpu22: cpu@16 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <22>; > > > + reg = <0x16>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu23: cpu@23 { > > > + cpu23: cpu@17 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <23>; > > > + reg = <0x17>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu24: cpu@24 { > > > + cpu24: cpu@18 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <24>; > > > + reg = <0x18>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu25: cpu@25 { > > > + cpu25: cpu@19 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <25>; > > > + reg = <0x19>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu26: cpu@26 { > > > + cpu26: cpu@1a { > > > compatible = "thead,c920", "riscv"; > > > - reg = <26>; > > > + reg = <0x1a>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu27: cpu@27 { > > > + cpu27: cpu@1b { > > > compatible = "thead,c920", "riscv"; > > > - reg = <27>; > > > + reg = <0x1b>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu28: cpu@28 { > > > + cpu28: cpu@1c { > > > compatible = "thead,c920", "riscv"; > > > - reg = <28>; > > > + reg = <0x1c>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu29: cpu@29 { > > > + cpu29: cpu@1d { > > > compatible = "thead,c920", "riscv"; > > > - reg = <29>; > > > + reg = <0x1d>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu30: cpu@30 { > > > + cpu30: cpu@1e { > > > compatible = "thead,c920", "riscv"; > > > - reg = <30>; > > > + reg = <0x1e>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu31: cpu@31 { > > > + cpu31: cpu@1f { > > > compatible = "thead,c920", "riscv"; > > > - reg = <31>; > > > + reg = <0x1f>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu32: cpu@32 { > > > + cpu32: cpu@20 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <32>; > > > + reg = <0x20>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu33: cpu@33 { > > > + cpu33: cpu@21 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <33>; > > > + reg = <0x21>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu34: cpu@34 { > > > + cpu34: cpu@22 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <34>; > > > + reg = <0x22>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu35: cpu@35 { > > > + cpu35: cpu@23 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <35>; > > > + reg = <0x23>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu36: cpu@36 { > > > + cpu36: cpu@24 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <36>; > > > + reg = <0x24>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu37: cpu@37 { > > > + cpu37: cpu@25 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <37>; > > > + reg = <0x25>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu38: cpu@38 { > > > + cpu38: cpu@26 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <38>; > > > + reg = <0x26>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu39: cpu@39 { > > > + cpu39: cpu@27 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <39>; > > > + reg = <0x27>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu40: cpu@40 { > > > + cpu40: cpu@28 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <40>; > > > + reg = <0x28>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu41: cpu@41 { > > > + cpu41: cpu@29 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <41>; > > > + reg = <0x29>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu42: cpu@42 { > > > + cpu42: cpu@2a { > > > compatible = "thead,c920", "riscv"; > > > - reg = <42>; > > > + reg = <0x2a>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu43: cpu@43 { > > > + cpu43: cpu@2b { > > > compatible = "thead,c920", "riscv"; > > > - reg = <43>; > > > + reg = <0x2b>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu44: cpu@44 { > > > + cpu44: cpu@2c { > > > compatible = "thead,c920", "riscv"; > > > - reg = <44>; > > > + reg = <0x2c>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu45: cpu@45 { > > > + cpu45: cpu@2d { > > > compatible = "thead,c920", "riscv"; > > > - reg = <45>; > > > + reg = <0x2d>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu46: cpu@46 { > > > + cpu46: cpu@2e { > > > compatible = "thead,c920", "riscv"; > > > - reg = <46>; > > > + reg = <0x2e>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu47: cpu@47 { > > > + cpu47: cpu@2f { > > > compatible = "thead,c920", "riscv"; > > > - reg = <47>; > > > + reg = <0x2f>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu48: cpu@48 { > > > + cpu48: cpu@30 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <48>; > > > + reg = <0x30>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu49: cpu@49 { > > > + cpu49: cpu@31 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <49>; > > > + reg = <0x31>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu50: cpu@50 { > > > + cpu50: cpu@32 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <50>; > > > + reg = <0x32>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu51: cpu@51 { > > > + cpu51: cpu@33 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <51>; > > > + reg = <0x33>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu52: cpu@52 { > > > + cpu52: cpu@34 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <52>; > > > + reg = <0x34>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu53: cpu@53 { > > > + cpu53: cpu@35 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <53>; > > > + reg = <0x35>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu54: cpu@54 { > > > + cpu54: cpu@36 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <54>; > > > + reg = <0x36>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu55: cpu@55 { > > > + cpu55: cpu@37 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <55>; > > > + reg = <0x37>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu56: cpu@56 { > > > + cpu56: cpu@38 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <56>; > > > + reg = <0x38>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu57: cpu@57 { > > > + cpu57: cpu@39 { > > > compatible = "thead,c920", "riscv"; > > > - reg = <57>; > > > + reg = <0x39>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu58: cpu@58 { > > > + cpu58: cpu@3a { > > > compatible = "thead,c920", "riscv"; > > > - reg = <58>; > > > + reg = <0x3a>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu59: cpu@59 { > > > + cpu59: cpu@3b { > > > compatible = "thead,c920", "riscv"; > > > - reg = <59>; > > > + reg = <0x3b>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu60: cpu@60 { > > > + cpu60: cpu@3c { > > > compatible = "thead,c920", "riscv"; > > > - reg = <60>; > > > + reg = <0x3c>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu61: cpu@61 { > > > + cpu61: cpu@3d { > > > compatible = "thead,c920", "riscv"; > > > - reg = <61>; > > > + reg = <0x3d>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu62: cpu@62 { > > > + cpu62: cpu@3e { > > > compatible = "thead,c920", "riscv"; > > > - reg = <62>; > > > + reg = <0x3e>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > @@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { > > > }; > > > }; > > > > > > - cpu63: cpu@63 { > > > + cpu63: cpu@3f { > > > compatible = "thead,c920", "riscv"; > > > - reg = <63>; > > > + reg = <0x3f>; > > > i-cache-block-size = <64>; > > > i-cache-size = <65536>; > > > i-cache-sets = <512>; > > > -- > > > 2.53.0 > > > > > > > > > -- > > Best Regards > > Guo Ren -- Best Regards Guo Ren ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address 2026-04-07 3:08 ` Guo Ren @ 2026-04-07 3:35 ` Inochi Amaoto 0 siblings, 0 replies; 9+ messages in thread From: Inochi Amaoto @ 2026-04-07 3:35 UTC (permalink / raw) To: Guo Ren, Inochi Amaoto Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Han Gao, Nutty Liu, Guodong Xu, Xiaoguang Xing, devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan, Longbin Li On Tue, Apr 07, 2026 at 11:08:19AM +0800, Guo Ren wrote: > On Tue, Apr 7, 2026 at 10:37 AM Inochi Amaoto <inochiama@gmail.com> wrote: > > > > On Tue, Apr 07, 2026 at 09:26:11AM +0800, Guo Ren wrote: > > > On Tue, Apr 7, 2026 at 7:27 AM Inochi Amaoto <inochiama@gmail.com> wrote: > > > > > > > > Previous the CPU unit address cpu of sg2044 use decimal, it is > > > > not following the general convention for unit addresses of the > > > > OF. Convent the unit address to hex to resolve this problem. > > > > > > > > The introduces a small ABI break for the CPU id, but it should > > > > affect nothing since there is no direct full-path reference to > > > > these CPU nodes. > > > > > > > > Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") > > > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > > > > Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/ > > > > > > Remove the Link tag, and add: > > > > > > Reviewed-by: Guo Ren <guoren@kernel.org> > > > > > > > This link provides the motivation for this patch, I think it will be > > fine for other to know why this patch is needed. > > The commit log already clearly describes the motivation: > - why we need to change from decimal to hex (OF unit address convention), > - the small ABI impact, > - and the Fixes tag. > > Adding a Link: tag that points back to the discussion thread doesn't > provide any additional information beyond what's already in the commit > message. In my opinion, the commit log is sufficient and > self-contained. > > Linus recently made it very clear that he wants us to stop adding > these kinds of low-value Link tags, as they just waste reviewers' > time: > > https://www.phoronix.com/news/Linus-Torvalds-No-Link-Tags > > Thanks for your detailed explanation. In this case the Link is indeed not valuable. I will remove it. Thanks. > > > > Regards, > > Inochi > > > > > > --- > > > > arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- > > > > 1 file changed, 118 insertions(+), 118 deletions(-) > > > > > > > > diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > > > > index 3135409c2149..f66a382c95bd 100644 > > > > --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > > > > +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi > > > > @@ -14,7 +14,7 @@ cpus { > > > > > > > > cpu0: cpu@0 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <0>; > > > > + reg = <0x0>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { > > > > > > > > cpu1: cpu@1 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <1>; > > > > + reg = <0x1>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { > > > > > > > > cpu2: cpu@2 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <2>; > > > > + reg = <0x2>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { > > > > > > > > cpu3: cpu@3 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <3>; > > > > + reg = <0x3>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { > > > > > > > > cpu4: cpu@4 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <4>; > > > > + reg = <0x4>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { > > > > > > > > cpu5: cpu@5 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <5>; > > > > + reg = <0x5>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { > > > > > > > > cpu6: cpu@6 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <6>; > > > > + reg = <0x6>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { > > > > > > > > cpu7: cpu@7 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <7>; > > > > + reg = <0x7>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { > > > > > > > > cpu8: cpu@8 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <8>; > > > > + reg = <0x8>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { > > > > > > > > cpu9: cpu@9 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <9>; > > > > + reg = <0x9>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu10: cpu@10 { > > > > + cpu10: cpu@a { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <10>; > > > > + reg = <0xa>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu11: cpu@11 { > > > > + cpu11: cpu@b { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <11>; > > > > + reg = <0xb>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu12: cpu@12 { > > > > + cpu12: cpu@c { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <12>; > > > > + reg = <0xc>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu13: cpu@13 { > > > > + cpu13: cpu@d { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <13>; > > > > + reg = <0xd>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu14: cpu@14 { > > > > + cpu14: cpu@e { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <14>; > > > > + reg = <0xe>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu15: cpu@15 { > > > > + cpu15: cpu@f { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <15>; > > > > + reg = <0xf>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu16: cpu@16 { > > > > + cpu16: cpu@10 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <16>; > > > > + reg = <0x10>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu17: cpu@17 { > > > > + cpu17: cpu@11 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <17>; > > > > + reg = <0x11>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu18: cpu@18 { > > > > + cpu18: cpu@12 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <18>; > > > > + reg = <0x12>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu19: cpu@19 { > > > > + cpu19: cpu@13 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <19>; > > > > + reg = <0x13>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu20: cpu@20 { > > > > + cpu20: cpu@14 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <20>; > > > > + reg = <0x14>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu21: cpu@21 { > > > > + cpu21: cpu@15 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <21>; > > > > + reg = <0x15>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu22: cpu@22 { > > > > + cpu22: cpu@16 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <22>; > > > > + reg = <0x16>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu23: cpu@23 { > > > > + cpu23: cpu@17 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <23>; > > > > + reg = <0x17>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu24: cpu@24 { > > > > + cpu24: cpu@18 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <24>; > > > > + reg = <0x18>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu25: cpu@25 { > > > > + cpu25: cpu@19 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <25>; > > > > + reg = <0x19>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu26: cpu@26 { > > > > + cpu26: cpu@1a { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <26>; > > > > + reg = <0x1a>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu27: cpu@27 { > > > > + cpu27: cpu@1b { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <27>; > > > > + reg = <0x1b>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu28: cpu@28 { > > > > + cpu28: cpu@1c { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <28>; > > > > + reg = <0x1c>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu29: cpu@29 { > > > > + cpu29: cpu@1d { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <29>; > > > > + reg = <0x1d>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu30: cpu@30 { > > > > + cpu30: cpu@1e { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <30>; > > > > + reg = <0x1e>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu31: cpu@31 { > > > > + cpu31: cpu@1f { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <31>; > > > > + reg = <0x1f>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu32: cpu@32 { > > > > + cpu32: cpu@20 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <32>; > > > > + reg = <0x20>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu33: cpu@33 { > > > > + cpu33: cpu@21 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <33>; > > > > + reg = <0x21>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu34: cpu@34 { > > > > + cpu34: cpu@22 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <34>; > > > > + reg = <0x22>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu35: cpu@35 { > > > > + cpu35: cpu@23 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <35>; > > > > + reg = <0x23>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu36: cpu@36 { > > > > + cpu36: cpu@24 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <36>; > > > > + reg = <0x24>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu37: cpu@37 { > > > > + cpu37: cpu@25 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <37>; > > > > + reg = <0x25>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu38: cpu@38 { > > > > + cpu38: cpu@26 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <38>; > > > > + reg = <0x26>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu39: cpu@39 { > > > > + cpu39: cpu@27 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <39>; > > > > + reg = <0x27>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu40: cpu@40 { > > > > + cpu40: cpu@28 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <40>; > > > > + reg = <0x28>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu41: cpu@41 { > > > > + cpu41: cpu@29 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <41>; > > > > + reg = <0x29>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu42: cpu@42 { > > > > + cpu42: cpu@2a { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <42>; > > > > + reg = <0x2a>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu43: cpu@43 { > > > > + cpu43: cpu@2b { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <43>; > > > > + reg = <0x2b>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu44: cpu@44 { > > > > + cpu44: cpu@2c { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <44>; > > > > + reg = <0x2c>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu45: cpu@45 { > > > > + cpu45: cpu@2d { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <45>; > > > > + reg = <0x2d>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu46: cpu@46 { > > > > + cpu46: cpu@2e { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <46>; > > > > + reg = <0x2e>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu47: cpu@47 { > > > > + cpu47: cpu@2f { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <47>; > > > > + reg = <0x2f>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu48: cpu@48 { > > > > + cpu48: cpu@30 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <48>; > > > > + reg = <0x30>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu49: cpu@49 { > > > > + cpu49: cpu@31 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <49>; > > > > + reg = <0x31>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu50: cpu@50 { > > > > + cpu50: cpu@32 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <50>; > > > > + reg = <0x32>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu51: cpu@51 { > > > > + cpu51: cpu@33 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <51>; > > > > + reg = <0x33>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu52: cpu@52 { > > > > + cpu52: cpu@34 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <52>; > > > > + reg = <0x34>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu53: cpu@53 { > > > > + cpu53: cpu@35 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <53>; > > > > + reg = <0x35>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu54: cpu@54 { > > > > + cpu54: cpu@36 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <54>; > > > > + reg = <0x36>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu55: cpu@55 { > > > > + cpu55: cpu@37 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <55>; > > > > + reg = <0x37>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu56: cpu@56 { > > > > + cpu56: cpu@38 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <56>; > > > > + reg = <0x38>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu57: cpu@57 { > > > > + cpu57: cpu@39 { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <57>; > > > > + reg = <0x39>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu58: cpu@58 { > > > > + cpu58: cpu@3a { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <58>; > > > > + reg = <0x3a>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu59: cpu@59 { > > > > + cpu59: cpu@3b { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <59>; > > > > + reg = <0x3b>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu60: cpu@60 { > > > > + cpu60: cpu@3c { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <60>; > > > > + reg = <0x3c>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu61: cpu@61 { > > > > + cpu61: cpu@3d { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <61>; > > > > + reg = <0x3d>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu62: cpu@62 { > > > > + cpu62: cpu@3e { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <62>; > > > > + reg = <0x3e>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > @@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { > > > > }; > > > > }; > > > > > > > > - cpu63: cpu@63 { > > > > + cpu63: cpu@3f { > > > > compatible = "thead,c920", "riscv"; > > > > - reg = <63>; > > > > + reg = <0x3f>; > > > > i-cache-block-size = <64>; > > > > i-cache-size = <65536>; > > > > i-cache-sets = <512>; > > > > -- > > > > 2.53.0 > > > > > > > > > > > > > -- > > > Best Regards > > > Guo Ren > > > > -- > Best Regards > Guo Ren ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/2] riscv: dts: sophgo: sg2042: use hex for CPU unit address 2026-04-06 23:26 [PATCH 0/2] riscv: dts: sophgo: Fix CPU unit address for SG2042/SG2044 Inochi Amaoto 2026-04-06 23:26 ` [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address Inochi Amaoto @ 2026-04-06 23:26 ` Inochi Amaoto 2026-04-07 1:26 ` Guo Ren 2026-04-07 16:31 ` Conor Dooley 1 sibling, 2 replies; 9+ messages in thread From: Inochi Amaoto @ 2026-04-06 23:26 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Inochi Amaoto, Han Gao, Nutty Liu, Guodong Xu, Guo Ren, Xiaoguang Xing Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan, Longbin Li Previous the CPU unit address cpu of sg2042 use decimal, it is not following the general convention for unit addresses of the OF. Convent the unit address to hex to resolve this problem. The introduces a small ABI break for the CPU id, but it should affect nothing since there is no direct full-path reference to these CPU nodes. Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/ --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++---------- 1 file changed, 118 insertions(+), 118 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index 509488eee432..fd8906b313d2 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -263,7 +263,7 @@ cpu0: cpu@0 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <0>; + reg = <0x0>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -291,7 +291,7 @@ cpu1: cpu@1 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <1>; + reg = <0x1>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -319,7 +319,7 @@ cpu2: cpu@2 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <2>; + reg = <0x2>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -347,7 +347,7 @@ cpu3: cpu@3 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <3>; + reg = <0x3>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -375,7 +375,7 @@ cpu4: cpu@4 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <4>; + reg = <0x4>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -403,7 +403,7 @@ cpu5: cpu@5 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <5>; + reg = <0x5>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -431,7 +431,7 @@ cpu6: cpu@6 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <6>; + reg = <0x6>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -459,7 +459,7 @@ cpu7: cpu@7 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <7>; + reg = <0x7>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -487,7 +487,7 @@ cpu8: cpu@8 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <8>; + reg = <0x8>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -515,7 +515,7 @@ cpu9: cpu@9 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <9>; + reg = <0x9>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller { }; }; - cpu10: cpu@10 { + cpu10: cpu@a { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -543,7 +543,7 @@ cpu10: cpu@10 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <10>; + reg = <0xa>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller { }; }; - cpu11: cpu@11 { + cpu11: cpu@b { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -571,7 +571,7 @@ cpu11: cpu@11 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <11>; + reg = <0xb>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller { }; }; - cpu12: cpu@12 { + cpu12: cpu@c { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -599,7 +599,7 @@ cpu12: cpu@12 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <12>; + reg = <0xc>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller { }; }; - cpu13: cpu@13 { + cpu13: cpu@d { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -627,7 +627,7 @@ cpu13: cpu@13 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <13>; + reg = <0xd>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller { }; }; - cpu14: cpu@14 { + cpu14: cpu@e { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -655,7 +655,7 @@ cpu14: cpu@14 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <14>; + reg = <0xe>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller { }; }; - cpu15: cpu@15 { + cpu15: cpu@f { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -683,7 +683,7 @@ cpu15: cpu@15 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <15>; + reg = <0xf>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller { }; }; - cpu16: cpu@16 { + cpu16: cpu@10 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -711,7 +711,7 @@ cpu16: cpu@16 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <16>; + reg = <0x10>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller { }; }; - cpu17: cpu@17 { + cpu17: cpu@11 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -739,7 +739,7 @@ cpu17: cpu@17 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <17>; + reg = <0x11>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller { }; }; - cpu18: cpu@18 { + cpu18: cpu@12 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -767,7 +767,7 @@ cpu18: cpu@18 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <18>; + reg = <0x12>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller { }; }; - cpu19: cpu@19 { + cpu19: cpu@13 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -795,7 +795,7 @@ cpu19: cpu@19 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <19>; + reg = <0x13>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller { }; }; - cpu20: cpu@20 { + cpu20: cpu@14 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -823,7 +823,7 @@ cpu20: cpu@20 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <20>; + reg = <0x14>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller { }; }; - cpu21: cpu@21 { + cpu21: cpu@15 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -851,7 +851,7 @@ cpu21: cpu@21 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <21>; + reg = <0x15>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller { }; }; - cpu22: cpu@22 { + cpu22: cpu@16 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -879,7 +879,7 @@ cpu22: cpu@22 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <22>; + reg = <0x16>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller { }; }; - cpu23: cpu@23 { + cpu23: cpu@17 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -907,7 +907,7 @@ cpu23: cpu@23 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <23>; + reg = <0x17>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller { }; }; - cpu24: cpu@24 { + cpu24: cpu@18 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -935,7 +935,7 @@ cpu24: cpu@24 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <24>; + reg = <0x18>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller { }; }; - cpu25: cpu@25 { + cpu25: cpu@19 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -963,7 +963,7 @@ cpu25: cpu@25 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <25>; + reg = <0x19>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller { }; }; - cpu26: cpu@26 { + cpu26: cpu@1a { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -991,7 +991,7 @@ cpu26: cpu@26 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <26>; + reg = <0x1a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller { }; }; - cpu27: cpu@27 { + cpu27: cpu@1b { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1019,7 +1019,7 @@ cpu27: cpu@27 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <27>; + reg = <0x1b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller { }; }; - cpu28: cpu@28 { + cpu28: cpu@1c { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1047,7 +1047,7 @@ cpu28: cpu@28 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <28>; + reg = <0x1c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller { }; }; - cpu29: cpu@29 { + cpu29: cpu@1d { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1075,7 +1075,7 @@ cpu29: cpu@29 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <29>; + reg = <0x1d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller { }; }; - cpu30: cpu@30 { + cpu30: cpu@1e { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1103,7 +1103,7 @@ cpu30: cpu@30 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <30>; + reg = <0x1e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller { }; }; - cpu31: cpu@31 { + cpu31: cpu@1f { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1131,7 +1131,7 @@ cpu31: cpu@31 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <31>; + reg = <0x1f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller { }; }; - cpu32: cpu@32 { + cpu32: cpu@20 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1159,7 +1159,7 @@ cpu32: cpu@32 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <32>; + reg = <0x20>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller { }; }; - cpu33: cpu@33 { + cpu33: cpu@21 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1187,7 +1187,7 @@ cpu33: cpu@33 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <33>; + reg = <0x21>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller { }; }; - cpu34: cpu@34 { + cpu34: cpu@22 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1215,7 +1215,7 @@ cpu34: cpu@34 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <34>; + reg = <0x22>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller { }; }; - cpu35: cpu@35 { + cpu35: cpu@23 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1243,7 +1243,7 @@ cpu35: cpu@35 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <35>; + reg = <0x23>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller { }; }; - cpu36: cpu@36 { + cpu36: cpu@24 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1271,7 +1271,7 @@ cpu36: cpu@36 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <36>; + reg = <0x24>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller { }; }; - cpu37: cpu@37 { + cpu37: cpu@25 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1299,7 +1299,7 @@ cpu37: cpu@37 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <37>; + reg = <0x25>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller { }; }; - cpu38: cpu@38 { + cpu38: cpu@26 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1327,7 +1327,7 @@ cpu38: cpu@38 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <38>; + reg = <0x26>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller { }; }; - cpu39: cpu@39 { + cpu39: cpu@27 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1355,7 +1355,7 @@ cpu39: cpu@39 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <39>; + reg = <0x27>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller { }; }; - cpu40: cpu@40 { + cpu40: cpu@28 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1383,7 +1383,7 @@ cpu40: cpu@40 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <40>; + reg = <0x28>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller { }; }; - cpu41: cpu@41 { + cpu41: cpu@29 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1411,7 +1411,7 @@ cpu41: cpu@41 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <41>; + reg = <0x29>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller { }; }; - cpu42: cpu@42 { + cpu42: cpu@2a { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1439,7 +1439,7 @@ cpu42: cpu@42 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <42>; + reg = <0x2a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller { }; }; - cpu43: cpu@43 { + cpu43: cpu@2b { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1467,7 +1467,7 @@ cpu43: cpu@43 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <43>; + reg = <0x2b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller { }; }; - cpu44: cpu@44 { + cpu44: cpu@2c { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1495,7 +1495,7 @@ cpu44: cpu@44 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <44>; + reg = <0x2c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller { }; }; - cpu45: cpu@45 { + cpu45: cpu@2d { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1523,7 +1523,7 @@ cpu45: cpu@45 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <45>; + reg = <0x2d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller { }; }; - cpu46: cpu@46 { + cpu46: cpu@2e { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1551,7 +1551,7 @@ cpu46: cpu@46 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <46>; + reg = <0x2e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller { }; }; - cpu47: cpu@47 { + cpu47: cpu@2f { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1579,7 +1579,7 @@ cpu47: cpu@47 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <47>; + reg = <0x2f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller { }; }; - cpu48: cpu@48 { + cpu48: cpu@30 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1607,7 +1607,7 @@ cpu48: cpu@48 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <48>; + reg = <0x30>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller { }; }; - cpu49: cpu@49 { + cpu49: cpu@31 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1635,7 +1635,7 @@ cpu49: cpu@49 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <49>; + reg = <0x31>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller { }; }; - cpu50: cpu@50 { + cpu50: cpu@32 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1663,7 +1663,7 @@ cpu50: cpu@50 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <50>; + reg = <0x32>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller { }; }; - cpu51: cpu@51 { + cpu51: cpu@33 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1691,7 +1691,7 @@ cpu51: cpu@51 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <51>; + reg = <0x33>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller { }; }; - cpu52: cpu@52 { + cpu52: cpu@34 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1719,7 +1719,7 @@ cpu52: cpu@52 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <52>; + reg = <0x34>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller { }; }; - cpu53: cpu@53 { + cpu53: cpu@35 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1747,7 +1747,7 @@ cpu53: cpu@53 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <53>; + reg = <0x35>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller { }; }; - cpu54: cpu@54 { + cpu54: cpu@36 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1775,7 +1775,7 @@ cpu54: cpu@54 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <54>; + reg = <0x36>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller { }; }; - cpu55: cpu@55 { + cpu55: cpu@37 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1803,7 +1803,7 @@ cpu55: cpu@55 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <55>; + reg = <0x37>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller { }; }; - cpu56: cpu@56 { + cpu56: cpu@38 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1831,7 +1831,7 @@ cpu56: cpu@56 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <56>; + reg = <0x38>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller { }; }; - cpu57: cpu@57 { + cpu57: cpu@39 { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1859,7 +1859,7 @@ cpu57: cpu@57 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <57>; + reg = <0x39>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller { }; }; - cpu58: cpu@58 { + cpu58: cpu@3a { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1887,7 +1887,7 @@ cpu58: cpu@58 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <58>; + reg = <0x3a>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller { }; }; - cpu59: cpu@59 { + cpu59: cpu@3b { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1915,7 +1915,7 @@ cpu59: cpu@59 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <59>; + reg = <0x3b>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller { }; }; - cpu60: cpu@60 { + cpu60: cpu@3c { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1943,7 +1943,7 @@ cpu60: cpu@60 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <60>; + reg = <0x3c>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller { }; }; - cpu61: cpu@61 { + cpu61: cpu@3d { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1971,7 +1971,7 @@ cpu61: cpu@61 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <61>; + reg = <0x3d>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller { }; }; - cpu62: cpu@62 { + cpu62: cpu@3e { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -1999,7 +1999,7 @@ cpu62: cpu@62 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <62>; + reg = <0x3e>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller { }; }; - cpu63: cpu@63 { + cpu63: cpu@3f { compatible = "thead,c920", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; @@ -2027,7 +2027,7 @@ cpu63: cpu@63 { "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; - reg = <63>; + reg = <0x3f>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; -- 2.53.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] riscv: dts: sophgo: sg2042: use hex for CPU unit address 2026-04-06 23:26 ` [PATCH 2/2] riscv: dts: sophgo: sg2042: " Inochi Amaoto @ 2026-04-07 1:26 ` Guo Ren 2026-04-07 16:31 ` Conor Dooley 1 sibling, 0 replies; 9+ messages in thread From: Guo Ren @ 2026-04-07 1:26 UTC (permalink / raw) To: Inochi Amaoto Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Han Gao, Nutty Liu, Guodong Xu, Xiaoguang Xing, devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan, Longbin Li On Tue, Apr 7, 2026 at 7:27 AM Inochi Amaoto <inochiama@gmail.com> wrote: > > Previous the CPU unit address cpu of sg2042 use decimal, it is > not following the general convention for unit addresses of the > OF. Convent the unit address to hex to resolve this problem. > > The introduces a small ABI break for the CPU id, but it should > affect nothing since there is no direct full-path reference to > these CPU nodes. > > Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > Link: https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/ I don't think this tag is necessary. For others: Reviewed-by: Guo Ren <guoren@kernel.org> > --- > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++---------- > 1 file changed, 118 insertions(+), 118 deletions(-) > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > index 509488eee432..fd8906b313d2 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > @@ -263,7 +263,7 @@ cpu0: cpu@0 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <0>; > + reg = <0x0>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -291,7 +291,7 @@ cpu1: cpu@1 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <1>; > + reg = <0x1>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -319,7 +319,7 @@ cpu2: cpu@2 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <2>; > + reg = <0x2>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -347,7 +347,7 @@ cpu3: cpu@3 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <3>; > + reg = <0x3>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -375,7 +375,7 @@ cpu4: cpu@4 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <4>; > + reg = <0x4>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -403,7 +403,7 @@ cpu5: cpu@5 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <5>; > + reg = <0x5>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -431,7 +431,7 @@ cpu6: cpu@6 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <6>; > + reg = <0x6>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -459,7 +459,7 @@ cpu7: cpu@7 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <7>; > + reg = <0x7>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -487,7 +487,7 @@ cpu8: cpu@8 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <8>; > + reg = <0x8>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -515,7 +515,7 @@ cpu9: cpu@9 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <9>; > + reg = <0x9>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller { > }; > }; > > - cpu10: cpu@10 { > + cpu10: cpu@a { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -543,7 +543,7 @@ cpu10: cpu@10 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <10>; > + reg = <0xa>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller { > }; > }; > > - cpu11: cpu@11 { > + cpu11: cpu@b { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -571,7 +571,7 @@ cpu11: cpu@11 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <11>; > + reg = <0xb>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller { > }; > }; > > - cpu12: cpu@12 { > + cpu12: cpu@c { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -599,7 +599,7 @@ cpu12: cpu@12 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <12>; > + reg = <0xc>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller { > }; > }; > > - cpu13: cpu@13 { > + cpu13: cpu@d { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -627,7 +627,7 @@ cpu13: cpu@13 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <13>; > + reg = <0xd>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller { > }; > }; > > - cpu14: cpu@14 { > + cpu14: cpu@e { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -655,7 +655,7 @@ cpu14: cpu@14 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <14>; > + reg = <0xe>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller { > }; > }; > > - cpu15: cpu@15 { > + cpu15: cpu@f { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -683,7 +683,7 @@ cpu15: cpu@15 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <15>; > + reg = <0xf>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller { > }; > }; > > - cpu16: cpu@16 { > + cpu16: cpu@10 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -711,7 +711,7 @@ cpu16: cpu@16 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <16>; > + reg = <0x10>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller { > }; > }; > > - cpu17: cpu@17 { > + cpu17: cpu@11 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -739,7 +739,7 @@ cpu17: cpu@17 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <17>; > + reg = <0x11>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller { > }; > }; > > - cpu18: cpu@18 { > + cpu18: cpu@12 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -767,7 +767,7 @@ cpu18: cpu@18 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <18>; > + reg = <0x12>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller { > }; > }; > > - cpu19: cpu@19 { > + cpu19: cpu@13 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -795,7 +795,7 @@ cpu19: cpu@19 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <19>; > + reg = <0x13>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller { > }; > }; > > - cpu20: cpu@20 { > + cpu20: cpu@14 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -823,7 +823,7 @@ cpu20: cpu@20 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <20>; > + reg = <0x14>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller { > }; > }; > > - cpu21: cpu@21 { > + cpu21: cpu@15 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -851,7 +851,7 @@ cpu21: cpu@21 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <21>; > + reg = <0x15>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller { > }; > }; > > - cpu22: cpu@22 { > + cpu22: cpu@16 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -879,7 +879,7 @@ cpu22: cpu@22 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <22>; > + reg = <0x16>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller { > }; > }; > > - cpu23: cpu@23 { > + cpu23: cpu@17 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -907,7 +907,7 @@ cpu23: cpu@23 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <23>; > + reg = <0x17>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller { > }; > }; > > - cpu24: cpu@24 { > + cpu24: cpu@18 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -935,7 +935,7 @@ cpu24: cpu@24 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <24>; > + reg = <0x18>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller { > }; > }; > > - cpu25: cpu@25 { > + cpu25: cpu@19 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -963,7 +963,7 @@ cpu25: cpu@25 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <25>; > + reg = <0x19>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller { > }; > }; > > - cpu26: cpu@26 { > + cpu26: cpu@1a { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -991,7 +991,7 @@ cpu26: cpu@26 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <26>; > + reg = <0x1a>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller { > }; > }; > > - cpu27: cpu@27 { > + cpu27: cpu@1b { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1019,7 +1019,7 @@ cpu27: cpu@27 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <27>; > + reg = <0x1b>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller { > }; > }; > > - cpu28: cpu@28 { > + cpu28: cpu@1c { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1047,7 +1047,7 @@ cpu28: cpu@28 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <28>; > + reg = <0x1c>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller { > }; > }; > > - cpu29: cpu@29 { > + cpu29: cpu@1d { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1075,7 +1075,7 @@ cpu29: cpu@29 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <29>; > + reg = <0x1d>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller { > }; > }; > > - cpu30: cpu@30 { > + cpu30: cpu@1e { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1103,7 +1103,7 @@ cpu30: cpu@30 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <30>; > + reg = <0x1e>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller { > }; > }; > > - cpu31: cpu@31 { > + cpu31: cpu@1f { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1131,7 +1131,7 @@ cpu31: cpu@31 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <31>; > + reg = <0x1f>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller { > }; > }; > > - cpu32: cpu@32 { > + cpu32: cpu@20 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1159,7 +1159,7 @@ cpu32: cpu@32 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <32>; > + reg = <0x20>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller { > }; > }; > > - cpu33: cpu@33 { > + cpu33: cpu@21 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1187,7 +1187,7 @@ cpu33: cpu@33 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <33>; > + reg = <0x21>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller { > }; > }; > > - cpu34: cpu@34 { > + cpu34: cpu@22 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1215,7 +1215,7 @@ cpu34: cpu@34 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <34>; > + reg = <0x22>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller { > }; > }; > > - cpu35: cpu@35 { > + cpu35: cpu@23 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1243,7 +1243,7 @@ cpu35: cpu@35 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <35>; > + reg = <0x23>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller { > }; > }; > > - cpu36: cpu@36 { > + cpu36: cpu@24 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1271,7 +1271,7 @@ cpu36: cpu@36 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <36>; > + reg = <0x24>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller { > }; > }; > > - cpu37: cpu@37 { > + cpu37: cpu@25 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1299,7 +1299,7 @@ cpu37: cpu@37 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <37>; > + reg = <0x25>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller { > }; > }; > > - cpu38: cpu@38 { > + cpu38: cpu@26 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1327,7 +1327,7 @@ cpu38: cpu@38 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <38>; > + reg = <0x26>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller { > }; > }; > > - cpu39: cpu@39 { > + cpu39: cpu@27 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1355,7 +1355,7 @@ cpu39: cpu@39 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <39>; > + reg = <0x27>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller { > }; > }; > > - cpu40: cpu@40 { > + cpu40: cpu@28 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1383,7 +1383,7 @@ cpu40: cpu@40 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <40>; > + reg = <0x28>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller { > }; > }; > > - cpu41: cpu@41 { > + cpu41: cpu@29 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1411,7 +1411,7 @@ cpu41: cpu@41 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <41>; > + reg = <0x29>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller { > }; > }; > > - cpu42: cpu@42 { > + cpu42: cpu@2a { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1439,7 +1439,7 @@ cpu42: cpu@42 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <42>; > + reg = <0x2a>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller { > }; > }; > > - cpu43: cpu@43 { > + cpu43: cpu@2b { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1467,7 +1467,7 @@ cpu43: cpu@43 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <43>; > + reg = <0x2b>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller { > }; > }; > > - cpu44: cpu@44 { > + cpu44: cpu@2c { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1495,7 +1495,7 @@ cpu44: cpu@44 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <44>; > + reg = <0x2c>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller { > }; > }; > > - cpu45: cpu@45 { > + cpu45: cpu@2d { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1523,7 +1523,7 @@ cpu45: cpu@45 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <45>; > + reg = <0x2d>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller { > }; > }; > > - cpu46: cpu@46 { > + cpu46: cpu@2e { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1551,7 +1551,7 @@ cpu46: cpu@46 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <46>; > + reg = <0x2e>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller { > }; > }; > > - cpu47: cpu@47 { > + cpu47: cpu@2f { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1579,7 +1579,7 @@ cpu47: cpu@47 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <47>; > + reg = <0x2f>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller { > }; > }; > > - cpu48: cpu@48 { > + cpu48: cpu@30 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1607,7 +1607,7 @@ cpu48: cpu@48 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <48>; > + reg = <0x30>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller { > }; > }; > > - cpu49: cpu@49 { > + cpu49: cpu@31 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1635,7 +1635,7 @@ cpu49: cpu@49 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <49>; > + reg = <0x31>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller { > }; > }; > > - cpu50: cpu@50 { > + cpu50: cpu@32 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1663,7 +1663,7 @@ cpu50: cpu@50 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <50>; > + reg = <0x32>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller { > }; > }; > > - cpu51: cpu@51 { > + cpu51: cpu@33 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1691,7 +1691,7 @@ cpu51: cpu@51 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <51>; > + reg = <0x33>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller { > }; > }; > > - cpu52: cpu@52 { > + cpu52: cpu@34 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1719,7 +1719,7 @@ cpu52: cpu@52 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <52>; > + reg = <0x34>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller { > }; > }; > > - cpu53: cpu@53 { > + cpu53: cpu@35 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1747,7 +1747,7 @@ cpu53: cpu@53 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <53>; > + reg = <0x35>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller { > }; > }; > > - cpu54: cpu@54 { > + cpu54: cpu@36 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1775,7 +1775,7 @@ cpu54: cpu@54 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <54>; > + reg = <0x36>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller { > }; > }; > > - cpu55: cpu@55 { > + cpu55: cpu@37 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1803,7 +1803,7 @@ cpu55: cpu@55 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <55>; > + reg = <0x37>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller { > }; > }; > > - cpu56: cpu@56 { > + cpu56: cpu@38 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1831,7 +1831,7 @@ cpu56: cpu@56 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <56>; > + reg = <0x38>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller { > }; > }; > > - cpu57: cpu@57 { > + cpu57: cpu@39 { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1859,7 +1859,7 @@ cpu57: cpu@57 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <57>; > + reg = <0x39>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller { > }; > }; > > - cpu58: cpu@58 { > + cpu58: cpu@3a { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1887,7 +1887,7 @@ cpu58: cpu@58 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <58>; > + reg = <0x3a>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller { > }; > }; > > - cpu59: cpu@59 { > + cpu59: cpu@3b { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1915,7 +1915,7 @@ cpu59: cpu@59 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <59>; > + reg = <0x3b>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller { > }; > }; > > - cpu60: cpu@60 { > + cpu60: cpu@3c { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1943,7 +1943,7 @@ cpu60: cpu@60 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <60>; > + reg = <0x3c>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller { > }; > }; > > - cpu61: cpu@61 { > + cpu61: cpu@3d { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1971,7 +1971,7 @@ cpu61: cpu@61 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <61>; > + reg = <0x3d>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller { > }; > }; > > - cpu62: cpu@62 { > + cpu62: cpu@3e { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -1999,7 +1999,7 @@ cpu62: cpu@62 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <62>; > + reg = <0x3e>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > @@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller { > }; > }; > > - cpu63: cpu@63 { > + cpu63: cpu@3f { > compatible = "thead,c920", "riscv"; > device_type = "cpu"; > riscv,isa = "rv64imafdc"; > @@ -2027,7 +2027,7 @@ cpu63: cpu@63 { > "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > - reg = <63>; > + reg = <0x3f>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > i-cache-sets = <512>; > -- > 2.53.0 > -- Best Regards Guo Ren ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] riscv: dts: sophgo: sg2042: use hex for CPU unit address 2026-04-06 23:26 ` [PATCH 2/2] riscv: dts: sophgo: sg2042: " Inochi Amaoto 2026-04-07 1:26 ` Guo Ren @ 2026-04-07 16:31 ` Conor Dooley 1 sibling, 0 replies; 9+ messages in thread From: Conor Dooley @ 2026-04-07 16:31 UTC (permalink / raw) To: Inochi Amaoto Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Han Gao, Nutty Liu, Guodong Xu, Guo Ren, Xiaoguang Xing, devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan, Longbin Li [-- Attachment #1: Type: text/plain, Size: 513 bytes --] On Tue, Apr 07, 2026 at 07:26:55AM +0800, Inochi Amaoto wrote: > Previous the CPU unit address cpu of sg2042 use decimal, it is > not following the general convention for unit addresses of the > OF. Convent the unit address to hex to resolve this problem. > > The introduces a small ABI break for the CPU id, but it should > affect nothing since there is no direct full-path reference to > these CPU nodes. I don't think node names are abi anyway. Acked-by: Conor Dooley <conor.dooley@microchip.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2026-04-07 16:31 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-04-06 23:26 [PATCH 0/2] riscv: dts: sophgo: Fix CPU unit address for SG2042/SG2044 Inochi Amaoto 2026-04-06 23:26 ` [PATCH 1/2] riscv: dts: sophgo: sg2044: use hex for CPU unit address Inochi Amaoto 2026-04-07 1:26 ` Guo Ren 2026-04-07 2:36 ` Inochi Amaoto 2026-04-07 3:08 ` Guo Ren 2026-04-07 3:35 ` Inochi Amaoto 2026-04-06 23:26 ` [PATCH 2/2] riscv: dts: sophgo: sg2042: " Inochi Amaoto 2026-04-07 1:26 ` Guo Ren 2026-04-07 16:31 ` Conor Dooley
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