Re: [PATCH net-next v2 1/2] dt-bindings: net: document Microchip PIC64-HPSC/HX MDIO controller

[Rob Herring <robh@kernel.org>]

On Mon, Mar 23, 2026 at 03:02:53PM -0700, Charles Perry wrote:
> This MDIO hardware is based on a Microsemi design supported in Linux by
> mdio-mscc-miim.c. However, The register interface is completely different
> with pic64hpsc, hence the need for separate documentation.
> 
> The hardware supports C22 and C45.
> 
> The documentation recommends an input clock of 156.25MHz and a prescaler
> of 39, which yields an MDIO clock of 1.95MHz.
> 
> The hardware supports an interrupt pin to signal transaction completion
> which is not strictly needed as the software can also poll a "TRIGGER"
> bit for this.
> 
> Signed-off-by: Charles Perry <charles.perry@microchip.com>
> ---
> 
> Notes:
>     Changes in v2:
>       - Make "clocks" and "interrupts" required (Andrew)
>       - Add a default value to "clock-frequency" (Andrew)
> 
>  .../net/microchip,pic64hpsc-mdio.yaml         | 68 +++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml b/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml
> new file mode 100644
> index 000000000000..d690afe3d3cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/microchip,pic64hpsc-mdio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip PIC64-HPSC/HX MDIO controller
> +
> +maintainers:
> +  - Charles Perry <charles.perry@microchip.com>
> +
> +description: |

Don't need '|' if no formatting to preserve.

> +  Microchip PIC64-HPSC/HX SoCs have two MDIO bus controller. This MDIO bus

s/controller/controllers/

Though how many instances there are is not really applicable to the 
binding unless there is some difference.

> +  controller supports C22 and C45 register access. It is named "MDIO Initiator"
> +  in the documentation.
> +
> +allOf:
> +  - $ref: mdio.yaml#
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: microchip,pic64hpsc-mdio
> +      - items:
> +          - const: microchip,pic64hx-mdio
> +          - const: microchip,pic64hpsc-mdio
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-frequency:
> +    default: 2500000
> +
> +  interrupts:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - interrupts
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    bus {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        mdio@4000C21E000 {

Unit-addresses are lower case hex.

> +            compatible = "microchip,pic64hpsc-mdio";
> +            reg = <0x400 0x0C21E000 0x0 0x1000>;

And generally we use lower case here too.

> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +            clocks = <&svc_clk>;
> +            interrupt-parent = <&saplic0>;
> +            interrupts = <168 IRQ_TYPE_LEVEL_HIGH>;
> +
> +            phy0: ethernet-phy@0 {

Drop unused labels.

> +                reg = <0>;
> +            };
> +        };
> +    };
> -- 
> 2.47.3
>