From: Krzysztof Kozlowski <krzk@kernel.org>
To: Geetha sowjanya <gakula@marvell.com>
Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, mark.rutland@arm.com,
will@kernel.org, krzk+dt@kernel.org
Subject: Re: [PATCH v4 1/2] dt-bindings: perf: marvell: Add CN20K DDR PMU binding
Date: Wed, 8 Apr 2026 09:09:09 +0200 [thread overview]
Message-ID: <20260408-fancy-slick-locust-ff68fe@quoll> (raw)
In-Reply-To: <20260407153511.4250-2-gakula@marvell.com>
On Tue, Apr 07, 2026 at 09:05:10PM +0530, Geetha sowjanya wrote:
> Marvell CN20K SoCs integrate a DDR Performance Monitoring Unit (PMU)
> associated with the DDR controller. The block provides hardware counters
> to monitor DDR traffic and performance events and is accessed via a
> dedicated MMIO region.
>
> The CN20K DDR PMU is functionally equivalent to the CN10K DDR PMU, with
> minor register offset differences. This binding documents the CN20K
> variant and introduces a specific compatible string to allow software
> to distinguish between the two implementations.
Drop last sentence, I already asked for that.
>
> Signed-off-by: Geetha sowjanya <gakula@marvell.com>
> ---
> .../bindings/perf/marvell-cn20k-ddr-pmu.yaml | 39 +++++++++++++++++++
Still wrong filename.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-04-08 7:09 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-07 15:35 [PATCH v4 0/2] perf: marvell: Add CN20K DDR PMU support Geetha sowjanya
2026-04-07 15:35 ` [PATCH v4 1/2] dt-bindings: perf: marvell: Add CN20K DDR PMU binding Geetha sowjanya
2026-04-08 7:09 ` Krzysztof Kozlowski [this message]
2026-04-10 9:28 ` Geethasowjanya Akula
2026-04-07 15:35 ` [PATCH v4 2/2] perf: marvell: Add CN20K DDR PMU support Geetha sowjanya
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