[PATCH v2 0/4] riscv: Add PCIe support for UltraRISC DP1000 SoC

[PATCH v2 0/4] riscv: Add PCIe support for UltraRISC DP1000 SoC

[Jia Wang]

This patch series adds PCIe controller support for the UltraRISC DP1000 SoC.
The DP1000 is an 8-core 64-bit RISC-V SoC based on UltraRISC CP100 cores,
supporting RV64GCBHX ISA with Hardware Virtualization and RISC-V H(v1.0)
Extension.

The PCIe controller is based on Synopsys DesignWare PCIe IP.
This series adds:
- Patch 1 adds the basic SoC family Kconfig support for UltraRISC platforms.
- Patch 2 adds the MAINTAINERS entry for the new driver.
- Patch 3 adds the device tree bindings documentation for the PCIe controller.
- Patch 4 introduces the PCIe host controller driver.

The patches have been tested on UltraRISC DP1000 development board with
various PCIe devices including NVMe SSDs and network cards, verifying
link establishment, enumeration, and basic data transfer.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
Changes in v2:
- Rebased onto v7.0-rc7.
- Patch 1:
   * Removed unnecessary 'depends' line.
   * Fixed help text indentation.
- Patch 2:
   * No changes.
- Patch 3:
   * Updated $ref to use 'snps,dw-pcie.yaml' as the base schema.
   * Add interrupts/interrupt-names (MSI + INTx).
   * Drop properties covered by generic DWC/PCI host bindings;
     update example accordingly.
   * Verified the schema passes 'make dt_binding_check' and 'yamllint'.
- Patch 4:
   * Update commit message.
   * Kconfig: switch PCIE_ULTRARISC to tristate; simplify help text.
   * Convert suspend/resume to dev_pm_ops and called
      `dw_pcie_suspend_noirq()` / `dw_pcie_resume_noirq()`.
   * Use FIELD_MODIFY(); adjust DWC header macros/comments.
   * Added empty `.pme_turn_off()` callback for DP1000 limitation.
   * Renamed link callback to `start_link`.
   * Switched to `module_platform_driver()`.
   * Formatting cleanups (headers order, spacing, variable naming,
     function names)
- Link to v1: https://patch.msgid.link/20260316-ultrarisc-pcie-v1-0-ef2946ede698@ultrarisc.com

---
Jia Wang (3):
      riscv: add UltraRISC SoC family Kconfig support
      MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding
      dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

Xincheng Zhang (1):
      PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver

 .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 103 +++++++++++
 MAINTAINERS                                        |   8 +
 arch/riscv/Kconfig.socs                            |   9 +
 drivers/pci/controller/dwc/Kconfig                 |  12 ++
 drivers/pci/controller/dwc/Makefile                |   1 +
 drivers/pci/controller/dwc/pcie-designware.h       |  22 +++
 drivers/pci/controller/dwc/pcie-ultrarisc.c        | 188 +++++++++++++++++++++
 7 files changed, 343 insertions(+)
---
base-commit: bfe62a454542cfad3379f6ef5680b125f41e20f4
change-id: 20260310-ultrarisc-pcie-494998763399

Best regards,
--  
Jia Wang <wangjia@ultrarisc.com>

[PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support

[Jia Wang]

The first SoC in the UltraRISC series is UR-DP1000, containing octa
UltraRISC C100 cores.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 arch/riscv/Kconfig.socs | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index d621b85dd63b..98708569ec6a 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -84,6 +84,15 @@ config ARCH_THEAD
 	help
 	  This enables support for the RISC-V based T-HEAD SoCs.
 
+config ARCH_ULTRARISC
+	bool "UltraRISC RISC-V SoCs"
+	help
+	  This enables support for UltraRISC SoC platform hardware,
+	  including boards based on the UR-DP1000.
+	  UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
+	  the RV64GCBHX ISA. It supports Hardware Virtualization
+	  and RISC-V RV64 ISA H(v1.0) Extension.
+
 config ARCH_VIRT
 	bool "QEMU Virt Machine"
 	select POWER_RESET

-- 
2.34.1

Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1353 bytes --]

On Tue, Apr 07, 2026 at 10:40:52AM +0800, Jia Wang wrote:
> The first SoC in the UltraRISC series is UR-DP1000, containing octa
> UltraRISC C100 cores.

Not gonna lie, I find it odd that pcie is where this platform starts
off, but sure. What's the plan for adding the rest of the platform?

> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  arch/riscv/Kconfig.socs | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index d621b85dd63b..98708569ec6a 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -84,6 +84,15 @@ config ARCH_THEAD
>  	help
>  	  This enables support for the RISC-V based T-HEAD SoCs.
>  
> +config ARCH_ULTRARISC
> +	bool "UltraRISC RISC-V SoCs"
> +	help
> +	  This enables support for UltraRISC SoC platform hardware,
> +	  including boards based on the UR-DP1000.

> +	  UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> +	  the RV64GCBHX ISA. It supports Hardware Virtualization
> +	  and RISC-V RV64 ISA H(v1.0) Extension.

Delete this section IMO, doesn't provide any real value. Don't need nor
want the marketing brochure in the help text. The first sentence is
sufficient.

> +
>  config ARCH_VIRT
>  	bool "QEMU Virt Machine"
>  	select POWER_RESET
> 
> -- 
> 2.34.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support

[Jia Wang]

On 2026-04-07 17:29 +0100, Conor Dooley wrote:
> On Tue, Apr 07, 2026 at 10:40:52AM +0800, Jia Wang wrote:
> > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > UltraRISC C100 cores.
> 
> Not gonna lie, I find it odd that pcie is where this platform starts
> off, but sure. What's the plan for adding the rest of the platform?
>

Hi Conor,

Thanks for the question.

Our next step is to upstream the pinctrl driver together with the related
DTS updates. The pinctrl series only affects the SoC’s low-speed peripheral
interfaces. For GMAC, SPI, I2C, and GPIO, we plan to use the existing
kernel drivers, so no new controller drivers are needed 
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  arch/riscv/Kconfig.socs | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index d621b85dd63b..98708569ec6a 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -84,6 +84,15 @@ config ARCH_THEAD
> >  	help
> >  	  This enables support for the RISC-V based T-HEAD SoCs.
> >  
> > +config ARCH_ULTRARISC
> > +	bool "UltraRISC RISC-V SoCs"
> > +	help
> > +	  This enables support for UltraRISC SoC platform hardware,
> > +	  including boards based on the UR-DP1000.
> 
> > +	  UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> > +	  the RV64GCBHX ISA. It supports Hardware Virtualization
> > +	  and RISC-V RV64 ISA H(v1.0) Extension.
> 
> Delete this section IMO, doesn't provide any real value. Don't need nor
> want the marketing brochure in the help text. The first sentence is
> sufficient.
>

I’ll drop the SoC description part from the Kconfig help text as you
suggested.
 
> > +
> >  config ARCH_VIRT
> >  	bool "QEMU Virt Machine"
> >  	select POWER_RESET
> > 
> > -- 
> > 2.34.1
> > 

Best regards,
Jia Wang

Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2372 bytes --]

On Wed, Apr 08, 2026 at 09:47:04AM +0800, Jia Wang wrote:
> On 2026-04-07 17:29 +0100, Conor Dooley wrote:
> > On Tue, Apr 07, 2026 at 10:40:52AM +0800, Jia Wang wrote:
> > > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > > UltraRISC C100 cores.
> > 
> > Not gonna lie, I find it odd that pcie is where this platform starts
> > off, but sure. What's the plan for adding the rest of the platform?
> >
> 
> Hi Conor,
> 
> Thanks for the question.
> 
> Our next step is to upstream the pinctrl driver together with the related
> DTS updates. The pinctrl series only affects the SoC’s low-speed peripheral
> interfaces. For GMAC, SPI, I2C, and GPIO, we plan to use the existing
> kernel drivers, so no new controller drivers are needed 

And clocks? pinctrl and clocks would be the bare minimum level of
support required before a platform should be merged. Obviously, you can
get device drivers for PCI etc etc merged without clock drivers, but the
initial dts should contain the clocks too.

> > > 
> > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > > ---
> > >  arch/riscv/Kconfig.socs | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > > 
> > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > index d621b85dd63b..98708569ec6a 100644
> > > --- a/arch/riscv/Kconfig.socs
> > > +++ b/arch/riscv/Kconfig.socs
> > > @@ -84,6 +84,15 @@ config ARCH_THEAD
> > >  	help
> > >  	  This enables support for the RISC-V based T-HEAD SoCs.
> > >  
> > > +config ARCH_ULTRARISC
> > > +	bool "UltraRISC RISC-V SoCs"
> > > +	help
> > > +	  This enables support for UltraRISC SoC platform hardware,
> > > +	  including boards based on the UR-DP1000.
> > 
> > > +	  UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> > > +	  the RV64GCBHX ISA. It supports Hardware Virtualization
> > > +	  and RISC-V RV64 ISA H(v1.0) Extension.
> > 
> > Delete this section IMO, doesn't provide any real value. Don't need nor
> > want the marketing brochure in the help text. The first sentence is
> > sufficient.
> >
> 
> I’ll drop the SoC description part from the Kconfig help text as you
> suggested.
>  
> > > +
> > >  config ARCH_VIRT
> > >  	bool "QEMU Virt Machine"
> > >  	select POWER_RESET
> > > 
> > > -- 
> > > 2.34.1
> > > 
> 
> Best regards,
> Jia Wang
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH v2 2/4] MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding

[Jia Wang]

Add a MAINTAINERS entry for the UltraRISC DP1000 PCIe host driver and its
DT binding.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index c3fe46d7c4bc..c8159670a14d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20582,6 +20582,14 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
 F:	drivers/pci/controller/plda/pcie-starfive.c
 
+PCIE DRIVER FOR ULTRARISC DP1000
+M:	Xincheng Zhang <zhangxincheng@ultrarisc.com>
+M:	Jia Wang <wangjia@ultrarisc.com>
+L:	linux-pci@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
+F:	drivers/pci/controller/dwc/pcie-ultrarisc.c
+
 PCIE ENDPOINT DRIVER FOR QUALCOMM
 M:	Manivannan Sadhasivam <mani@kernel.org>
 L:	linux-pci@vger.kernel.org

-- 
2.34.1

Re: [PATCH v2 2/4] MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding

[Krzysztof Kozlowski]

On Tue, Apr 07, 2026 at 10:40:53AM +0800, Jia Wang wrote:
> Add a MAINTAINERS entry for the UltraRISC DP1000 PCIe host driver and its
> DT binding.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  MAINTAINERS | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c3fe46d7c4bc..c8159670a14d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20582,6 +20582,14 @@ S:	Maintained
>  F:	Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
>  F:	drivers/pci/controller/plda/pcie-starfive.c
>  
> +PCIE DRIVER FOR ULTRARISC DP1000
> +M:	Xincheng Zhang <zhangxincheng@ultrarisc.com>
> +M:	Jia Wang <wangjia@ultrarisc.com>
> +L:	linux-pci@vger.kernel.org
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml

There is no such file.

This is not supposed to be a separate commit.

> +F:	drivers/pci/controller/dwc/pcie-ultrarisc.c

No such file.

Best regards,
Krzysztof

Re: [PATCH v2 2/4] MAINTAINERS: Add entry for the UltraRISC DP1000 PCIe controller driver and its DT binding

[Jia Wang]

On 2026-04-07 09:44 +0200, Krzysztof Kozlowski wrote:
> On Tue, Apr 07, 2026 at 10:40:53AM +0800, Jia Wang wrote:
> > Add a MAINTAINERS entry for the UltraRISC DP1000 PCIe host driver and its
> > DT binding.
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  MAINTAINERS | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index c3fe46d7c4bc..c8159670a14d 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -20582,6 +20582,14 @@ S:	Maintained
> >  F:	Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> >  F:	drivers/pci/controller/plda/pcie-starfive.c
> >  
> > +PCIE DRIVER FOR ULTRARISC DP1000
> > +M:	Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > +M:	Jia Wang <wangjia@ultrarisc.com>
> > +L:	linux-pci@vger.kernel.org
> > +S:	Maintained
> > +F:	Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> 
> There is no such file.
> 
> This is not supposed to be a separate commit.
>

Hi Krzysztof,

Thanks for the review.

In the next version I will fold this patch into the commit that adds the
actual driver and DT binding, so the referenced files will exist.
 
> > +F:	drivers/pci/controller/dwc/pcie-ultrarisc.c
> 
> No such file.
> 
> Best regards,
> Krzysztof
> 
> 

Best regards,
Jia Wang

[PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang]

Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 103 +++++++++++++++++++++
 1 file changed, 103 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
new file mode 100644
index 000000000000..d0517130e127
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UltraRISC DP1000 PCIe Host Controller
+
+description: |
+  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
+  This binding describes the UltraRISC specific extensions to the base
+  DesignWare PCIe binding.
+
+maintainers:
+  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
+  - Jia Wang <wangjia@ultrarisc.com>
+
+allOf:
+  - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+properties:
+  compatible:
+    const: ultrarisc,dp1000-pcie
+
+  reg:
+    items:
+      - description: Data Bus Interface (DBI) registers.
+      - description: PCIe configuration space region.
+
+  reg-names:
+    items:
+      - const: dbi
+      - const: config
+
+  num-lanes:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [4, 16]
+    description: Number of lanes to use.
+
+  max-link-speed:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    const: 4
+    description: Maximum PCIe link speed supported.
+
+  interrupts:
+    description: List of interrupt specifiers used by the controller
+    items:
+      - description: MSI interrupt
+      - description: Legacy INTA interrupt
+      - description: Legacy INTB interrupt
+      - description: Legacy INTC interrupt
+      - description: Legacy INTD interrupt
+
+  interrupt-names:
+    items:
+      - const: msi
+      - const: inta
+      - const: intb
+      - const: intc
+      - const: intd
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pcie_x16: pcie@21000000 {
+        compatible = "ultrarisc,dp1000-pcie";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        #interrupt-cells = <1>;
+        reg = <0x0 0x21000000 0x0 0x01000000>,
+              <0x0 0x4fff0000 0x0 0x00010000>;
+        reg-names = "dbi", "config";
+        device_type = "pci";
+        dma-coherent;
+        bus-range = <0x0 0xff>;
+        num-lanes = <16>;
+        ranges = <0x81000000  0x0 0x4fbf0000  0x0 0x4fbf0000  0x0 0x00400000>,
+                 <0x82000000  0x0 0x40000000  0x0 0x40000000  0x0 0x0fbf0000>,
+                 <0xc3000000 0x40 0x00000000 0x40 0x00000000  0xd 0x00000000>;
+
+        max-link-speed = <4>;
+        interrupt-parent = <&plic>;
+        interrupts = <43>, <44>, <45>, <46>, <47>;
+        interrupt-names = "msi", "inta", "intb", "intc", "intd";
+        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+        interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,
+                        <0x0 0x0 0x0 0x2 &plic 45>,
+                        <0x0 0x0 0x0 0x3 &plic 46>,
+                        <0x0 0x0 0x0 0x4 &plic 47>;
+      };
+    };

-- 
2.34.1

Re: [PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Krzysztof Kozlowski]

On Tue, Apr 07, 2026 at 10:40:54AM +0800, Jia Wang wrote:
> Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 103 +++++++++++++++++++++
>  1 file changed, 103 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> new file mode 100644
> index 000000000000..d0517130e127
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> @@ -0,0 +1,103 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: UltraRISC DP1000 PCIe Host Controller
> +
> +description: |

Do not need '|' unless you need to preserve formatting.

> +  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
> +  This binding describes the UltraRISC specific extensions to the base
> +  DesignWare PCIe binding.

Drop sentence. Do not describe in description what the binding
describes. It's circular / repetitive. Just describe that.

> +
> +maintainers:
> +  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
> +  - Jia Wang <wangjia@ultrarisc.com>
> +
> +allOf:
> +  - $ref: /schemas/pci/snps,dw-pcie.yaml#
> +
> +properties:
> +  compatible:
> +    const: ultrarisc,dp1000-pcie
> +
> +  reg:
> +    items:
> +      - description: Data Bus Interface (DBI) registers.
> +      - description: PCIe configuration space region.
> +
> +  reg-names:
> +    items:
> +      - const: dbi
> +      - const: config
> +
> +  num-lanes:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [4, 16]
> +    description: Number of lanes to use.
> +
> +  max-link-speed:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    const: 4

If const then deducible from the compatible. Drop the property.

> +    description: Maximum PCIe link speed supported.
> +
> +  interrupts:
> +    description: List of interrupt specifiers used by the controller

Drop description. Obvious.

> +    items:
> +      - description: MSI interrupt
> +      - description: Legacy INTA interrupt
> +      - description: Legacy INTB interrupt
> +      - description: Legacy INTC interrupt
> +      - description: Legacy INTD interrupt
> +
> +  interrupt-names:
> +    items:
> +      - const: msi
> +      - const: inta
> +      - const: intb
> +      - const: intc
> +      - const: intd
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - interrupt-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    soc {
> +      #address-cells = <2>;
> +      #size-cells = <2>;
> +
> +      pcie_x16: pcie@21000000 {

Drop unused label

> +        compatible = "ultrarisc,dp1000-pcie";

reg, names and ranges go here. Please follow DTS coding style.

> +        #address-cells = <3>;
> +        #size-cells = <2>;
> +        #interrupt-cells = <1>;
> +        reg = <0x0 0x21000000 0x0 0x01000000>,
> +              <0x0 0x4fff0000 0x0 0x00010000>;
> +        reg-names = "dbi", "config";
> +        device_type = "pci";
> +        dma-coherent;
> +        bus-range = <0x0 0xff>;
> +        num-lanes = <16>;
> +        ranges = <0x81000000  0x0 0x4fbf0000  0x0 0x4fbf0000  0x0 0x00400000>,
> +                 <0x82000000  0x0 0x40000000  0x0 0x40000000  0x0 0x0fbf0000>,
> +                 <0xc3000000 0x40 0x00000000 0x40 0x00000000  0xd 0x00000000>;
> +
> +        max-link-speed = <4>;

Drop, compatible defines this.

Best regards,
Krzysztof

Re: [PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang]

On 2026-04-07 09:50 +0200, Krzysztof Kozlowski wrote:
> On Tue, Apr 07, 2026 at 10:40:54AM +0800, Jia Wang wrote:
> > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 103 +++++++++++++++++++++
> >  1 file changed, 103 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> > new file mode 100644
> > index 000000000000..d0517130e127
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> > @@ -0,0 +1,103 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: UltraRISC DP1000 PCIe Host Controller
> > +
> > +description: |
> 
> Do not need '|' unless you need to preserve formatting.
>

Hi Krzysztof,

Thanks. I’ll remove the `|` in v3.
 
> > +  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
> > +  This binding describes the UltraRISC specific extensions to the base
> > +  DesignWare PCIe binding.
> 
> Drop sentence. Do not describe in description what the binding
> describes. It's circular / repetitive. Just describe that.
> 

Will simplify the description to a single concise statement in v3.

> > +
> > +maintainers:
> > +  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
> > +  - Jia Wang <wangjia@ultrarisc.com>
> > +
> > +allOf:
> > +  - $ref: /schemas/pci/snps,dw-pcie.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    const: ultrarisc,dp1000-pcie
> > +
> > +  reg:
> > +    items:
> > +      - description: Data Bus Interface (DBI) registers.
> > +      - description: PCIe configuration space region.
> > +
> > +  reg-names:
> > +    items:
> > +      - const: dbi
> > +      - const: config
> > +
> > +  num-lanes:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [4, 16]
> > +    description: Number of lanes to use.
> > +
> > +  max-link-speed:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    const: 4
> 
> If const then deducible from the compatible. Drop the property.
> 

Will replace `const: 4` with `maximum: 4` in v3.

> > +    description: Maximum PCIe link speed supported.
> > +
> > +  interrupts:
> > +    description: List of interrupt specifiers used by the controller
> 
> Drop description. Obvious.
> 

Will drop the description in v3.

> > +    items:
> > +      - description: MSI interrupt
> > +      - description: Legacy INTA interrupt
> > +      - description: Legacy INTB interrupt
> > +      - description: Legacy INTC interrupt
> > +      - description: Legacy INTD interrupt
> > +
> > +  interrupt-names:
> > +    items:
> > +      - const: msi
> > +      - const: inta
> > +      - const: intb
> > +      - const: intc
> > +      - const: intd
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +  - interrupts
> > +  - interrupt-names
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > +  - |
> > +    soc {
> > +      #address-cells = <2>;
> > +      #size-cells = <2>;
> > +
> > +      pcie_x16: pcie@21000000 {
> 
> Drop unused label
> 

Will drop it in v3.

> > +        compatible = "ultrarisc,dp1000-pcie";
> 
> reg, names and ranges go here. Please follow DTS coding style.
> 

Will update the example to include reg, reg-names, and ranges following DTS
coding style in v3.

> > +        #address-cells = <3>;
> > +        #size-cells = <2>;
> > +        #interrupt-cells = <1>;
> > +        reg = <0x0 0x21000000 0x0 0x01000000>,
> > +              <0x0 0x4fff0000 0x0 0x00010000>;
> > +        reg-names = "dbi", "config";
> > +        device_type = "pci";
> > +        dma-coherent;
> > +        bus-range = <0x0 0xff>;
> > +        num-lanes = <16>;
> > +        ranges = <0x81000000  0x0 0x4fbf0000  0x0 0x4fbf0000  0x0 0x00400000>,
> > +                 <0x82000000  0x0 0x40000000  0x0 0x40000000  0x0 0x0fbf0000>,
> > +                 <0xc3000000 0x40 0x00000000 0x40 0x00000000  0xd 0x00000000>;
> > +
> > +        max-link-speed = <4>;
> 
> Drop, compatible defines this.
> 
> Best regards,
> Krzysztof
> 
> 

Best regards,
Jia Wang

Re: [PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Krzysztof Kozlowski]

On 08/04/2026 05:34, Jia Wang wrote:
>>> +  max-link-speed:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    const: 4
>>
>> If const then deducible from the compatible. Drop the property.
>>
> 
> Will replace `const: 4` with `maximum: 4` in v3.

Why? Wasn't maximum link speed fixed to 4?


Best regards,
Krzysztof

Re: [PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Jia Wang]

On 2026-04-08 08:28 +0200, Krzysztof Kozlowski wrote:
> On 08/04/2026 05:34, Jia Wang wrote:
> >>> +  max-link-speed:
> >>> +    $ref: /schemas/types.yaml#/definitions/uint32
> >>> +    const: 4
> >>
> >> If const then deducible from the compatible. Drop the property.
> >>
> > 
> > Will replace `const: 4` with `maximum: 4` in v3.
> 
> Why? Wasn't maximum link speed fixed to 4?
>

Just to make sure I fully understand: since the maximum link speed is a
fixed hardware property and is implied by the compatible, we should drop
the `max-link-speed` property from the binding.

In that case, should I set `pci->max_link_speed = 4` in the driver during
probe? I want to make sure this is the correct way to handle it.
 
> 
> Best regards,
> Krzysztof
> 

Best regards,
Jia Wang

Re: [PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Krzysztof Kozlowski]

On 08/04/2026 08:43, Jia Wang wrote:
> On 2026-04-08 08:28 +0200, Krzysztof Kozlowski wrote:
>> On 08/04/2026 05:34, Jia Wang wrote:
>>>>> +  max-link-speed:
>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>>> +    const: 4
>>>>
>>>> If const then deducible from the compatible. Drop the property.
>>>>
>>>
>>> Will replace `const: 4` with `maximum: 4` in v3.
>>
>> Why? Wasn't maximum link speed fixed to 4?
>>
> 
> Just to make sure I fully understand: since the maximum link speed is a
> fixed hardware property and is implied by the compatible, we should drop
> the `max-link-speed` property from the binding.
> 
> In that case, should I set `pci->max_link_speed = 4` in the driver during
> probe? I want to make sure this is the correct way to handle it.
>  

Yes

Best regards,
Krzysztof

[PATCH v2 4/4] PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver

[Jia Wang]

From: Xincheng Zhang <zhangxincheng@ultrarisc.com>

Add DP1000 SoC PCIe Root Complex driver.

Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 drivers/pci/controller/dwc/Kconfig           |  12 ++
 drivers/pci/controller/dwc/Makefile          |   1 +
 drivers/pci/controller/dwc/pcie-designware.h |  22 ++++
 drivers/pci/controller/dwc/pcie-ultrarisc.c  | 188 +++++++++++++++++++++++++++
 4 files changed, 223 insertions(+)

diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index d0aa031397fa..06f7d98259cd 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -548,4 +548,16 @@ config PCIE_VISCONTI_HOST
 	  Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
 	  This driver supports TMPV7708 SoC.
 
+config PCIE_ULTRARISC
+	tristate "UltraRISC PCIe host controller"
+	depends on ARCH_ULTRARISC || COMPILE_TEST
+	select PCIE_DW_HOST
+	select PCI_MSI
+	default y if ARCH_ULTRARISC
+	help
+	  Enables support for the PCIe controller in the UltraRISC SoC.
+	  This driver supports UR-DP1000 SoC.
+	  By default, this symbol is enabled when ARCH_ULTRARISC is active,
+	  requiring no further configuration on that platform.
+
 endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 67ba59c02038..884c46b78e01 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
 obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
 obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
 obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
+obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o
 
 # The following drivers are for devices that use the generic ACPI
 # pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ae6389dd9caa..88dcb0e7943a 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -69,6 +69,8 @@
 
 /* Synopsys-specific PCIe configuration registers */
 #define PCIE_PORT_FORCE			0x708
+/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */
+#define PORT_LINK_NUM_MASK		GENMASK(7, 0)
 #define PORT_FORCE_DO_DESKEW_FOR_SRIS	BIT(23)
 
 #define PCIE_PORT_AFR			0x70C
@@ -96,6 +98,26 @@
 #define PCIE_PORT_LANE_SKEW		0x714
 #define PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)
 
+/*
+ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number
+ * Register.
+ * This register holds the ack frequency, latency, replay, fast link
+ * scaling timers, and max function number values.
+ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor.
+ *   0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us).
+ *     When the LTSSM is in Config or L12 Entry State, 1ms
+ *     timer is 2us, 2ms timer is 4us and 3ms timer is 6us.
+ *   0x1 (SF_256): Scaling Factor is 256 (1ms is 4us)
+ *   0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)
+ *   0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)
+ */
+#define PCIE_TIMER_CTRL_MAX_FUNC_NUM	0x718
+#define PORT_FLT_SF_MASK	GENMASK(30, 29)
+#define PORT_FLT_SF_VAL_1024	0x0
+#define PORT_FLT_SF_VAL_256	0x1
+#define PORT_FLT_SF_VAL_64	0x2
+#define PORT_FLT_SF_VAL_16	0x3
+
 #define PCIE_PORT_DEBUG0		0x728
 #define PORT_LOGIC_LTSSM_STATE_MASK	0x3f
 #define PORT_LOGIC_LTSSM_STATE_L0	0x11
diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
new file mode 100644
index 000000000000..0da37efa8680
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DWC PCIe RC driver for UltraRISC DP1000 SoC
+ *
+ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#include "pcie-designware.h"
+
+#define PCIE_CUS_CORE          0x400000
+
+#define LTSSM_ENABLE           BIT(7)
+#define FAST_LINK_MODE         BIT(12)
+#define HOLD_PHY_RST           BIT(14)
+#define L1SUB_DISABLE          BIT(15)
+
+struct ultrarisc_pcie {
+	struct dw_pcie *pci;
+	u32 irq_mask[MAX_MSI_CTRLS];
+};
+
+static struct pci_ops ultrarisc_pci_ops = {
+	.map_bus = dw_pcie_own_conf_map_bus,
+	.read = pci_generic_config_read32,
+	.write = pci_generic_config_write32,
+};
+
+static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)
+{
+	struct pci_host_bridge *bridge = pp->bridge;
+
+	bridge->ops = &ultrarisc_pci_ops;
+
+	return 0;
+}
+
+static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp)
+{
+	/*
+	 * DP1000 does not support sending PME_Turn_Off from the RC.
+	 * Keep this callback empty to skip the generic MSG TLP path.
+	 */
+}
+
+static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = {
+	.init = ultrarisc_pcie_host_init,
+	.pme_turn_off = ultrarisc_pcie_pme_turn_off,
+};
+
+static int ultrarisc_pcie_start_link(struct dw_pcie *pci)
+{
+	u32 val;
+	u8 cap_exp;
+
+	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
+	val &= ~FAST_LINK_MODE;
+	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);
+	FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64);
+	dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);
+
+	cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);
+	FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT);
+	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
+	FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0);
+	dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
+
+	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);
+	FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val, 0x6);
+	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val);
+
+	val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
+	val &= ~(HOLD_PHY_RST | L1SUB_DISABLE);
+	val |= LTSSM_ENABLE;
+	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
+
+	return 0;
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+	.start_link = ultrarisc_pcie_start_link,
+};
+
+static int ultrarisc_pcie_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ultrarisc_pcie *pcie;
+	struct dw_pcie *pci;
+	struct dw_pcie_rp *pp;
+	int ret;
+
+	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+	if (!pcie)
+		return -ENOMEM;
+
+	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+	if (!pci)
+		return -ENOMEM;
+
+	pci->dev = dev;
+	pci->ops = &dw_pcie_ops;
+
+	/* Set a default value suitable for at most 16 in and 16 out windows */
+	pci->atu_size = SZ_8K;
+
+	pcie->pci = pci;
+
+	pp = &pci->pp;
+
+	platform_set_drvdata(pdev, pcie);
+
+	pp->irq = platform_get_irq(pdev, 1);
+	if (pp->irq < 0)
+		return pp->irq;
+
+	pp->num_vectors = MAX_MSI_IRQS;
+	/* No L2/L3 Ready indication is available on this platform. */
+	pp->skip_l23_ready = true;
+	pp->ops = &ultrarisc_pcie_host_ops;
+
+	ret = dw_pcie_host_init(pp);
+	if (ret) {
+		dev_err(dev, "Failed to initialize host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int ultrarisc_pcie_suspend_noirq(struct device *dev)
+{
+	struct ultrarisc_pcie *pcie = dev_get_drvdata(dev);
+	struct dw_pcie *pci = pcie->pci;
+
+	return dw_pcie_suspend_noirq(pci);
+}
+
+static int ultrarisc_pcie_resume_noirq(struct device *dev)
+{
+	struct ultrarisc_pcie *pcie = dev_get_drvdata(dev);
+	struct dw_pcie *pci = pcie->pci;
+
+	return dw_pcie_resume_noirq(pci);
+}
+
+static const struct dev_pm_ops ultrarisc_pcie_pm_ops = {
+	NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq,
+				  ultrarisc_pcie_resume_noirq)
+};
+
+static const struct of_device_id ultrarisc_pcie_of_match[] = {
+	{
+		.compatible = "ultrarisc,dp1000-pcie",
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match);
+
+static struct platform_driver ultrarisc_pcie_driver = {
+	.driver = {
+		.name	= "ultrarisc-pcie",
+		.of_match_table = ultrarisc_pcie_of_match,
+		.suppress_bind_attrs = true,
+		.pm = &ultrarisc_pcie_pm_ops,
+	},
+	.probe = ultrarisc_pcie_probe,
+};
+module_platform_driver(ultrarisc_pcie_driver);
+
+MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller");
+MODULE_LICENSE("GPL");

-- 
2.34.1