From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Cc: tomm.merciai@gmail.com, geert@linux-m68k.org,
linux-renesas-soc@vger.kernel.org, biju.das.jz@bp.renesas.com,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Magnus Damm <magnus.damm@gmail.com>,
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v6 10/21] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC
Date: Wed, 8 Apr 2026 17:16:38 +0300 [thread overview]
Message-ID: <20260408141638.GA1965119@killaraus.ideasonboard.com> (raw)
In-Reply-To: <dafdbdcf-98db-473c-8122-296af1922e6c@bp.renesas.com>
On Wed, Apr 08, 2026 at 04:02:14PM +0200, Tommaso Merciai wrote:
> Hi Laurent,
> Thanks for your review.
>
> On 4/8/26 14:24, Laurent Pinchart wrote:
> > On Wed, Apr 08, 2026 at 12:36:55PM +0200, Tommaso Merciai wrote:
> >> The RZ/G3E SoC has 2 LCD controllers (LCDC), each containing a Frame
> >> Compression Processor (FCPVD), a Video Signal Processor (VSPD), and a
> >> Display Unit (DU).
> >>
> >> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> >> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> >>
> >> Add a new SoC-specific compatible string 'renesas,r9a09g047-du'.
> >>
> >> Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" to
> >> allow up to four output ports, and explicitly disable port@2 and port@3
> >> for existing SoCs that do not expose them.
> >>
> >> Describe the four output ports of the RZ/G3E DU:
> >>
> >> - port@0: DSI (available on both LCDC instances)
> >> - port@1: DPAD / parallel RGB (LCDC1 only)
> >> - port@2: LVDS channel 0 (LCDC0 only)
> >> - port@3: LVDS channel 1 (available on both LCDC instances)
> >>
> >> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> >> ---
> >> v5->v6:
> >> - Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
> >> explicitly disable port@2 and port@3 for existing SoCs that do not expose
> >> them.
> >> - Reworked ports numbering + improved/fixed ports descriptions in the
> >> bindings documentation.
> >> - Improved commit body.
> >>
> >> v4->v5:
> >> - Dropped renesas,id property and updated bindings
> >> accordingly.
> >>
> >> v2->v3:
> >> - No changes.
> >>
> >> v2->v3:
> >> - No changes.
> >>
> >> v1->v2:
> >> - Use single compatible string instead of multiple compatible strings
> >> for the two DU instances, leveraging a 'renesas,id' property to
> >> differentiate between DU0 and DU1.
> >> - Updated commit message accordingly.
> >>
> >> .../bindings/display/renesas,rzg2l-du.yaml | 30 ++++++++++++++++++-
> >> 1 file changed, 29 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >> index 5add3b832eab..32da0b5ec88c 100644
> >> --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >> @@ -20,6 +20,7 @@ properties:
> >> - enum:
> >> - renesas,r9a07g043u-du # RZ/G2UL
> >> - renesas,r9a07g044-du # RZ/G2{L,LC}
> >> + - renesas,r9a09g047-du # RZ/G3E
> >> - renesas,r9a09g057-du # RZ/V2H(P)
> >> - items:
> >> - enum:
> >> @@ -61,7 +62,7 @@ properties:
> >> model-dependent. Each port shall have a single endpoint.
> >>
> >> patternProperties:
> >> - "^port@[0-1]$":
> >> + "^port@[0-3]$":
> >> $ref: /schemas/graph.yaml#/properties/port
> >> unevaluatedProperties: false
> >>
> >> @@ -103,6 +104,8 @@ allOf:
> >> port@0:
> >> description: DPI
> >> port@1: false
> >> + port@2: false
> >> + port@3: false
> >>
> >> required:
> >> - port@0
> >> @@ -119,6 +122,8 @@ allOf:
> >> description: DSI
> >> port@1:
> >> description: DPI
> >> + port@2: false
> >> + port@3: false
> >>
> >> required:
> >> - port@0
> >> @@ -135,9 +140,32 @@ allOf:
> >> port@0:
> >> description: DSI
> >> port@1: false
> >> + port@2: false
> >> + port@3: false
> >>
> >> required:
> >> - port@0
> >> + - if:
> >> + properties:
> >> + compatible:
> >> + contains:
> >> + const: renesas,r9a09g047-du
> >> + then:
> >> + properties:
> >> + ports:
> >> + properties:
> >> + port@0:
> >> + description: DSI
> >> + port@1:
> >> + description: DPAD
> >> + port@2:
> >> + description: LVDS, Channel 0
> >> + port@3:
> >> + description: LVDS, Channel 1
> >> +
> >> + required:
> >> + - port@0
> >> + - port@3
> >
> > Why are ports 1 and 2 not required ?
>
> About this we had a similar discussion on v5[0]
> We are using the same compatible and:
>
> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> |
> --> then has:
> port@0
> port@2
> port@3
>
>
> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> |
> --> then has:
> port@0
> port@1
> port@3
Ah yes, I forget there are two LCDC instances with different output
configurations.
Something still looks a bit weird to me though. For LCDC1, which
supports a single LVDS channel, you use the port described as the second
LVDS channel. Is there a reason not to use port@2 ?
> Then port@1 is required for DU1 but not for DU0.
> Same port@2 is required for DU0 but not for DU1.
>
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/ca022fdbba5236c36e0cb3095db4c31e8e0cb1b8.1770996493.git.tommaso.merciai.xr@bp.renesas.com/
>
> >>
> >> examples:
> >> # RZ/G2L DU
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2026-04-08 14:16 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-08 10:36 [PATCH v6 00/21] Add support for DU and DSI on the Renesas RZ/G3E SoC Tommaso Merciai
2026-04-08 10:36 ` [PATCH v6 01/21] clk: renesas: rzv2h: Add PLLDSI clk mux support Tommaso Merciai
2026-04-08 13:19 ` Geert Uytterhoeven
2026-04-08 10:36 ` [PATCH v6 02/21] clk: renesas: r9a09g047: Add CLK_PLLETH_LPCLK support Tommaso Merciai
2026-04-08 10:36 ` [PATCH v6 03/21] clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks Tommaso Merciai
2026-04-08 10:36 ` [PATCH v6 04/21] clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks Tommaso Merciai
2026-04-08 10:36 ` [PATCH v6 05/21] clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks Tommaso Merciai
2026-04-08 10:36 ` [PATCH v6 06/21] clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK Tommaso Merciai
2026-04-08 13:23 ` Geert Uytterhoeven
2026-04-08 10:36 ` [PATCH v6 07/21] clk: renesas: r9a09g047: Add support for DSI clocks and resets Tommaso Merciai
2026-04-08 10:36 ` [PATCH v6 08/21] clk: renesas: r9a09g047: Add support for LCDC{0,1} " Tommaso Merciai
2026-04-08 10:36 ` [PATCH v6 09/21] dt-bindings: display: renesas,rzg2l-du: Refuse port@1 for RZ/G2UL Tommaso Merciai
2026-04-08 12:21 ` Laurent Pinchart
2026-04-08 10:36 ` [PATCH v6 10/21] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC Tommaso Merciai
2026-04-08 12:24 ` Laurent Pinchart
2026-04-08 14:02 ` Tommaso Merciai
2026-04-08 14:16 ` Laurent Pinchart [this message]
2026-04-08 14:44 ` Tommaso Merciai
2026-04-08 15:00 ` Laurent Pinchart
2026-04-08 10:36 ` [PATCH v6 11/21] dt-bindings: display: bridge: renesas,dsi: " Tommaso Merciai
2026-04-08 10:36 ` [PATCH v6 12/21] drm: renesas: rz-du: mipi_dsi: Add out_port to OF data Tommaso Merciai
2026-04-08 12:30 ` Laurent Pinchart
2026-04-08 10:36 ` [PATCH v6 13/21] drm: renesas: rz-du: mipi_dsi: Add RZ_MIPI_DSI_FEATURE_GPO0R feature Tommaso Merciai
2026-04-08 12:31 ` Laurent Pinchart
2026-04-08 14:12 ` Tommaso Merciai
2026-04-08 14:17 ` Laurent Pinchart
2026-04-08 14:58 ` Tommaso Merciai
2026-04-08 15:08 ` Laurent Pinchart
2026-04-08 10:36 ` [PATCH v6 14/21] drm: renesas: rz-du: mipi_dsi: Add support for RZ/G3E Tommaso Merciai
2026-04-08 10:37 ` [PATCH v6 15/21] drm: renesas: rz-du: Add RZ/G3E support Tommaso Merciai
2026-04-08 10:37 ` [PATCH v6 16/21] media: dt-bindings: media: renesas,vsp1: Document RZ/G3E Tommaso Merciai
2026-04-08 10:52 ` Laurent Pinchart
2026-04-08 10:37 ` [PATCH v6 17/21] media: dt-bindings: media: renesas,fcp: Document RZ/G3E SoC Tommaso Merciai
2026-04-08 10:53 ` Laurent Pinchart
2026-04-08 10:37 ` [PATCH v6 18/21] arm64: dts: renesas: r9a09g047: Add fcpvd{0,1} nodes Tommaso Merciai
2026-04-08 11:32 ` Laurent Pinchart
2026-04-08 10:37 ` [PATCH v6 19/21] arm64: dts: renesas: r9a09g047: Add vspd{0,1} nodes Tommaso Merciai
2026-04-08 11:33 ` Laurent Pinchart
2026-04-08 10:37 ` [PATCH v6 20/21] arm64: dts: renesas: r9a09g047: Add DU{0,1} and DSI nodes Tommaso Merciai
2026-04-08 12:11 ` Laurent Pinchart
2026-04-08 10:37 ` [PATCH v6 21/21] arm64: dts: renesas: r9a09g047e57-smarc: Enable DU0 and DSI support Tommaso Merciai
2026-04-08 13:01 ` Geert Uytterhoeven
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