Re: [PATCH 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions and port labels

Konrad Dybcio
2026-04-07T11:05:36Z

On 4/4/26 11:50 AM, Joe Sandom via B4 Relay wrote:
> From: Joe Sandom <jsandom@axon.com>
>
> Add the MHI register regions to the pcie0 and pcie1 controller nodes
> so that the MHI bus layer can access controller registers directly.
>
> Also add labels to the root port nodes (pcie0_port0, pcie1_port0) to
> allow board DTS files to reference them for adding endpoint devices
> to each pcie root port.
>
> Signed-off-by: Joe Sandom <jsandom@axon.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..d4caf4d00832d7f1e8f65bf2bc873cddadc42168 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1964,8 +1964,9 @@ pcie0: pcie@1c00000 {
> <0 0x60000000 0 0xf1d>,
> <0 0x60000f20 0 0xa8>,
> <0 0x60001000 0 0x1000>,
> - <0 0x60100000 0 0x100000>;
> - reg-names = "parf", "dbi", "elbi", "atu", "config";
> + <0 0x60100000 0 0x100000>,
> + <0 0x01C03000 0 0x1000>;

lowercase hex please, both places

> + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";

Since you're touching this part of the file anyway and others asked for
more changes.. could you please break up the reg-names that you're
editing such that there's one entry per line and they're aligned on
the opening quote, i.e.

reg-names = "foo",
"bar",
...

?

FWIW the reg ranges you added are OK

Konrad