Re: [PATCH 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions and port labels

Dmitry Baryshkov
2026-04-04T21:07:20Z

On Sat, Apr 04, 2026 at 10:50:54AM +0100, Joe Sandom via B4 Relay wrote:
> From: Joe Sandom <jsandom@axon.com>
>
> Add the MHI register regions to the pcie0 and pcie1 controller nodes
> so that the MHI bus layer can access controller registers directly.
>
> Also add labels to the root port nodes (pcie0_port0, pcie1_port0) to
> allow board DTS files to reference them for adding endpoint devices
> to each pcie root port.

Two separate changes, please.

>
> Signed-off-by: Joe Sandom <jsandom@axon.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..d4caf4d00832d7f1e8f65bf2bc873cddadc42168 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1964,8 +1964,9 @@ pcie0: pcie@1c00000 {
> <0 0x60000000 0 0xf1d>,
> <0 0x60000f20 0 0xa8>,
> <0 0x60001000 0 0x1000>,
> - <0 0x60100000 0 0x100000>;
> - reg-names = "parf", "dbi", "elbi", "atu", "config";
> + <0 0x60100000 0 0x100000>,
> + <0 0x01C03000 0 0x1000>;

Lowercase the hex, align vertically.

> + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
> #address-cells = <3>;
> #size-cells = <2>;
> ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
> @@ -2092,7 +2093,7 @@ opp-16000000-3 {
> };
> };
>
> - pcieport0: pcie@0 {
> + pcie0_port0: pcie@0 {
> device_type = "pci";
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
> @@ -2138,8 +2139,9 @@ pcie1: pcie@1c08000 {
> <0x0 0x40000000 0x0 0xf1d>,
> <0x0 0x40000f20 0x0 0xa8>,
> <0x0 0x40001000 0x0 0x1000>,
> - <0x0 0x40100000 0x0 0x100000>;
> - reg-names = "parf", "dbi", "elbi", "atu", "config";
> + <0x0 0x40100000 0x0 0x100000>,
> + <0x0 0x01C0B000 0x0 0x1000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
> #address-cells = <3>;
> #size-cells = <2>;
> ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> @@ -2288,7 +2290,7 @@ opp-32000000-4 {
> };
> };
>
> - pcie@0 {
> + pcie1_port0: pcie@0 {
> device_type = "pci";
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
>
> --
> 2.34.1
>
>

--
With best wishes
Dmitry