From: Joe Sandom <jsandom@axon.com>
To: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions
Date: Thu, 9 Apr 2026 12:41:01 +0100 [thread overview]
Message-ID: <20260409114101.ta543li356mpv6q7@linaro> (raw)
In-Reply-To: <8ed5aeb8-98fb-4b87-a6a9-983e4fa91db5@linaro.org>
On Tue, Apr 07, 2026 at 07:38:54PM +0200, Neil Armstrong wrote:
> On 4/7/26 17:46, Joe Sandom wrote:
> > Add the MHI register regions to the pcie0 and pcie1 controller nodes
> > so that the MHI bus layer can access controller registers directly.
>
> Can you elaborate more on that ? Looking at the current implementation,
> the pcie host driver only uses the mhi memory zone to show the transition
> count in debugfs.
>
hmm yeah, you're right. As you said, it's only used for transition count
currently. I'll make sure the commit message is clearer in v3.
> Neil
>
> >
> > Signed-off-by: Joe Sandom <jsandom@axon.com>
> > ---
> > arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++----
> > 1 file changed, 16 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..055ca931c04859f3a312eb9921aeb7a8cc676822 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > @@ -1964,8 +1964,14 @@ pcie0: pcie@1c00000 {
> > <0 0x60000000 0 0xf1d>,
> > <0 0x60000f20 0 0xa8>,
> > <0 0x60001000 0 0x1000>,
> > - <0 0x60100000 0 0x100000>;
> > - reg-names = "parf", "dbi", "elbi", "atu", "config";
> > + <0 0x60100000 0 0x100000>,
> > + <0 0x01c03000 0 0x1000>;
> > + reg-names = "parf",
> > + "dbi",
> > + "elbi",
> > + "atu",
> > + "config",
> > + "mhi";
> > #address-cells = <3>;
> > #size-cells = <2>;
> > ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
> > @@ -2138,8 +2144,14 @@ pcie1: pcie@1c08000 {
> > <0x0 0x40000000 0x0 0xf1d>,
> > <0x0 0x40000f20 0x0 0xa8>,
> > <0x0 0x40001000 0x0 0x1000>,
> > - <0x0 0x40100000 0x0 0x100000>;
> > - reg-names = "parf", "dbi", "elbi", "atu", "config";
> > + <0x0 0x40100000 0x0 0x100000>,
> > + <0x0 0x01c0b000 0x0 0x1000>;
> > + reg-names = "parf",
> > + "dbi",
> > + "elbi",
> > + "atu",
> > + "config",
> > + "mhi";
> > #address-cells = <3>;
> > #size-cells = <2>;
> > ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> >
>
next prev parent reply other threads:[~2026-04-09 11:41 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-07 15:46 [PATCH v2 0/5] arm64: dts: qcom: add QCS8550 RB5Gen2 support Joe Sandom via B4 Relay
2026-04-07 15:46 ` [PATCH v2 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions Joe Sandom via B4 Relay
2026-04-07 17:38 ` Neil Armstrong
2026-04-09 11:41 ` Joe Sandom [this message]
2026-04-07 15:46 ` [PATCH v2 2/5] arm64: dts: qcom: sm8550: add PCIe port labels Joe Sandom via B4 Relay
2026-04-07 17:32 ` Neil Armstrong
2026-04-09 1:45 ` Dmitry Baryshkov
2026-04-07 15:46 ` [PATCH v2 3/5] arm64: dts: qcom: sm8550: move IPA properties to SoC device tree Joe Sandom via B4 Relay
2026-04-09 1:45 ` Dmitry Baryshkov
2026-04-07 15:46 ` [PATCH v2 4/5] dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board Joe Sandom via B4 Relay
2026-04-07 15:46 ` [PATCH v2 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support Joe Sandom via B4 Relay
2026-04-08 9:57 ` Konrad Dybcio
2026-04-08 12:35 ` Neil Armstrong
2026-04-08 13:15 ` Konrad Dybcio
2026-04-09 11:23 ` Joe Sandom
2026-04-09 11:24 ` Konrad Dybcio
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260409114101.ta543li356mpv6q7@linaro \
--to=jsandom@axon.com \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=neil.armstrong@linaro.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox