From: Joe Sandom <jsandom@axon.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
Date: Thu, 9 Apr 2026 12:46:23 +0100 [thread overview]
Message-ID: <20260409114623.u4zyacth7g4eo35d@linaro> (raw)
In-Reply-To: <lusy4sd2q22tvtvzgbb3pbpxauy5ym46ojjtpjq43wyzn72yxy@uxcggqladbnl>
On Thu, Apr 09, 2026 at 04:56:06PM +0530, Manivannan Sadhasivam wrote:
> On Thu, Apr 09, 2026 at 11:04:55AM +0100, Joe Sandom wrote:
> > On Tue, Apr 07, 2026 at 09:44:34PM +0530, Manivannan Sadhasivam wrote:
> > > On Tue, Apr 07, 2026 at 12:39:25PM +0100, Joe Sandom wrote:
> > >
> > > [...]
> > >
> > > > > > +&pcie0 {
> > > > > > + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
> > > > > > + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
> > > > > > +
> > > > > > + pinctrl-0 = <&pcie0_default_state>;
> > > > > > + pinctrl-names = "default";
> > > > > > +
> > > > > > + iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
> > > > > > + <0x100 &apps_smmu 0x1401 0x1>,
> > > > > > + <0x208 &apps_smmu 0x1402 0x1>,
> > > > > > + <0x210 &apps_smmu 0x1403 0x1>,
> > > > > > + <0x218 &apps_smmu 0x1404 0x1>,
> > > > > > + <0x300 &apps_smmu 0x1407 0x1>,
> > > > > > + <0x400 &apps_smmu 0x1408 0x1>,
> > > > > > + <0x500 &apps_smmu 0x140c 0x1>,
> > > > > > + <0x501 &apps_smmu 0x140e 0x1>;
> > > > > > +
> > > > > > + /delete-property/ msi-map;
> > > > >
> > > > > Why?
> > > > I tried extending the msi-map to cover the RIDs from the QPS615
> > > > PCIe switch (matching the iommu-map entries), but this caused
> > > > ITS MAPD command timeouts.
> > >
> > > I'm not aware of any specific issue with ITS on this chipset. At what time did
> > > you see the timeout? During probe?
> > So when I set msi-map to match the iommu-map entries, I got this;
> > [ 0.000000] ITS [mem 0x17140000-0x1717ffff]
> > [ 11.085152] ath12k_wifi7_pci 0001:04:00.0: BAR 0 assigned
> > [ 11.115762] ath12k_wifi7_pci 0001:04:00.0: Wi-Fi 7 Hardware name: wcn7850 hw2.0
> > [ 11.153632] ath12k_wifi7_pci 0001:04:00.0: MSI vectors: 16
> > [ 11.252398] mhi mhi0: Requested to power ON
> > .........
> > [ 101.596274] mhi mhi0: Wait for device to enter SBL or Mission mode
> > [ 101.603098] ath12k_wifi7_pci 0001:04:00.0: failed to set mhi state: POWER_ON(2)
> > [ 101.610632] ath12k_wifi7_pci 0001:04:00.0: failed to start mhi: -110
> > [ 101.617171] ath12k_wifi7_pci 0001:04:00.0: failed to power up :-110
> > [ 101.794431] ath12k_wifi7_pci 0001:04:00.0: probe failed with error -110
> > [ 103.158872] ITS queue timeout (12640 12609)
> > [ 103.163183] ITS cmd its_build_mapd_cmd failed
> >
> > With msi-map removed, I got this;
> > [ 11.469642] ath12k_wifi7_pci 0001:04:00.0: BAR 0 assigned
> > [ 11.490059] ath12k_wifi7_pci 0001:04:00.0: Wi-Fi 7 Hardware name: wcn7850 hw2.0
> > [ 11.497787] ath12k_wifi7_pci 0001:04:00.0: MSI vectors: 16
> > [ 11.559958] mhi mhi0: Requested to power ON
> > [ 11.567375] mhi mhi0: Power on setup success
> > [ 11.693069] mhi mhi0: Wait for device to enter SBL or Mission mode
> > [ 12.185946] ath12k_wifi7_pci 0001:04:00.0: chip_id 0x2 ... soc_id 0x40170200
> > [ 12.482168] ath12k_wifi7_pci 0001:04:00.0 wlP1p4s0: renamed from wlan0
>
> Thanks for the logs. I also checked internally and learned that the timeout is
> due to Gunyah limiting the devices per-port. On SM8550, it currently only
> allows 2 devices per RC instance to save the memory footprint. So when you
> connect a PCIe switch which exposes more than two devices (1 USP + (1+) DSPs),
> you'll run out of ITS mapping in Gunyah, leading to these timeouts.
>
> So either you need to modify Gunyah to allow more devices per-port or switch to
> iMSI-RX which you are already doing.
>
Makes sense! Thanks for checking Mani, good to get to the bottom of that.
I'll leave it as is for now and will look into modifying Gunyah
separately.
In v3 I'll update the commit message to reflect your findings
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
Thanks,
Joe
prev parent reply other threads:[~2026-04-09 11:46 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-04 9:50 [PATCH 0/5] arm64: dts: qcom: add QCS8550 RB5Gen2 support Joe Sandom via B4 Relay
2026-04-04 9:50 ` [PATCH 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions and port labels Joe Sandom via B4 Relay
2026-04-04 21:07 ` Dmitry Baryshkov
2026-04-07 8:53 ` Joe Sandom
2026-04-07 11:05 ` Konrad Dybcio
2026-04-07 11:43 ` Joe Sandom
2026-04-04 9:50 ` [PATCH 2/5] arm64: dts: qcom: sm8550-hdk: update PCIe port label reference Joe Sandom via B4 Relay
2026-04-04 21:07 ` Dmitry Baryshkov
2026-04-07 8:55 ` Joe Sandom
2026-04-05 8:11 ` Krzysztof Kozlowski
2026-04-04 9:50 ` [PATCH 3/5] arm64: dts: qcom: sm8550-qrd: " Joe Sandom via B4 Relay
2026-04-04 9:50 ` [PATCH 4/5] dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board Joe Sandom via B4 Relay
2026-04-05 8:11 ` Krzysztof Kozlowski
2026-04-04 9:50 ` [PATCH 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support Joe Sandom via B4 Relay
2026-04-04 21:20 ` Dmitry Baryshkov
2026-04-07 11:39 ` Joe Sandom
2026-04-07 15:01 ` Dmitry Baryshkov
2026-04-07 15:43 ` Joe Sandom
2026-04-07 16:14 ` Manivannan Sadhasivam
2026-04-09 10:04 ` Joe Sandom
2026-04-09 11:26 ` Manivannan Sadhasivam
2026-04-09 11:46 ` Joe Sandom [this message]
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