[PATCH v6 18/21] arm64: dts: renesas: r9a09g047: Add fcpvd{0,1} nodes

Tommaso Merciai
2026-04-08T10:40:17Z

Add fcpvd{0,1} nodes to RZ/G3E SoC DTSI.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v5->v6:
- No changes.

v4->v5:
- No changes.

v3->v4:
- No changes.

v2->v3:
- No changes.

v1->v2:
- Squashed fcpvd0 and fcpvd1 patches into a single patch.
- Collected tags.

arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 95a4e30a064d..3115ab4b050f 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -1584,6 +1584,30 @@ csi2cru: endpoint@0 {
};
};
};
+
+ fcpvd0: fcp@16470000 {
+ compatible = "renesas,r9a09g047-fcpvd",
+ "renesas,fcpv";
+ reg = <0 0x16470000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ resets = <&cpg 0xdc>;
+ power-domains = <&cpg>;
+ };
+
+ fcpvd1: fcp@164a0000 {
+ compatible = "renesas,r9a09g047-fcpvd",
+ "renesas,fcpv";
+ reg = <0 0x164a0000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0x1a8>,
+ <&cpg CPG_MOD 0x1a9>,
+ <&cpg CPG_MOD 0x1aa>;
+ clock-names = "aclk", "pclk", "vclk";
+ resets = <&cpg 0x11e>;
+ power-domains = <&cpg>;
+ };
};

stmmac_axi_setup: stmmac-axi-config {
--
2.43.0