[PATCH v1 5/5] irqchip: starfive: Implement irq_set_type and irq_ack hooks

Changhuang Liang
2026-04-10T10:34:09Z

Add irq_set_type hook to support configuring interrupt trigger types
(level high/low, edge rising/falling) for the JHB100 interrupt controller.
Also add irq_ack hook as required by handle_edge_irq.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/irqchip/irq-starfive-jhb100-intc.c | 72 ++++++++++++++++++++++
1 file changed, 72 insertions(+)

diff --git a/drivers/irqchip/irq-starfive-jhb100-intc.c b/drivers/irqchip/irq-starfive-jhb100-intc.c
index d5ecbb603a58..d34f960b0770 100644
--- a/drivers/irqchip/irq-starfive-jhb100-intc.c
+++ b/drivers/irqchip/irq-starfive-jhb100-intc.c
@@ -9,6 +9,7 @@

#include <linux/bitops.h>
#include <linux/clk.h>
+#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
@@ -18,12 +19,20 @@
#include <linux/reset.h>
#include <linux/spinlock.h>

+#define STARFIVE_INTC_SRC_TYPE(n) (0x04 + ((n) * 0x20))
#define STARFIVE_INTC_SRC_CLEAR(n) (0x10 + ((n) * 0x20))
#define STARFIVE_INTC_SRC_MASK(n) (0x14 + ((n) * 0x20))
#define STARFIVE_INTC_SRC_INT(n) (0x1c + ((n) * 0x20))

+#define STARFIVE_INTC_TRIGGER_MASK 0x3
+#define STARFIVE_INTC_TRIGGER_HIGH 0
+#define STARFIVE_INTC_TRIGGER_LOW 1
+#define STARFIVE_INTC_TRIGGER_POSEDGE 2
+#define STARFIVE_INTC_TRIGGER_NEGEDGE 3
+
#define STARFIVE_INTC_NUM 2
#define STARFIVE_INTC_SRC_IRQ_NUM 32
+#define STARFIVE_INTC_TYPE_NUM 16

struct starfive_irq_chip {
void __iomem *base;
@@ -31,6 +40,17 @@ struct starfive_irq_chip {
raw_spinlock_t lock;
};

+static void starfive_intc_mod(struct starfive_irq_chip *irqc, u32 reg,
+ u32 mask, u32 data)
+{
+ u32 value;
+
+ value = ioread32(irqc->base + reg) & ~mask;
+ data &= mask;
+ data |= value;
+ iowrite32(data, irqc->base + reg);
+}
+
static void starfive_intc_bit_set(struct starfive_irq_chip *irqc,
u32 reg, u32 bit_mask)
{
@@ -77,10 +97,62 @@ static void starfive_intc_mask(struct irq_data *d)
raw_spin_unlock(&irqc->lock);
}

+static void starfive_intc_ack(struct irq_data *d)
+{
+ /* for handle_edge_irq, nothing to do */
+}
+
+static int starfive_intc_set_type(struct irq_data *d, unsigned int type)
+{
+ struct starfive_irq_chip *irqc = irq_data_get_irq_chip_data(d);
+ u32 i, bitpos, ty_pos, ty_shift, tmp;
+
+ i = d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM;
+ bitpos = d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM;
+ ty_pos = bitpos / STARFIVE_INTC_TYPE_NUM;
+ ty_shift = (bitpos % STARFIVE_INTC_TYPE_NUM) * 2;
+
+ switch (type) {
+ case IRQF_TRIGGER_LOW:
+ tmp = STARFIVE_INTC_TRIGGER_LOW << ty_shift;
+ irq_set_handler_locked(d, handle_level_irq);
+ break;
+ case IRQF_TRIGGER_HIGH:
+ tmp = STARFIVE_INTC_TRIGGER_HIGH << ty_shift;
+ irq_set_handler_locked(d, handle_level_irq);
+ break;
+ case IRQF_TRIGGER_FALLING:
+ tmp = STARFIVE_INTC_TRIGGER_NEGEDGE << ty_shift;
+ irq_set_handler_locked(d, handle_edge_irq);
+ break;
+ case IRQF_TRIGGER_RISING:
+ tmp = STARFIVE_INTC_TRIGGER_POSEDGE << ty_shift;
+ irq_set_handler_locked(d, handle_edge_irq);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ raw_spin_lock(&irqc->lock);
+
+ starfive_intc_mod(irqc, STARFIVE_INTC_SRC_TYPE(i) + 4 * ty_pos,
+ STARFIVE_INTC_TRIGGER_MASK << ty_shift, tmp);
+
+ /* Once the type is updated, clear interrupt can help to reset the type value */
+ starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(bitpos));
+ starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(bitpos));
+
+ raw_spin_unlock(&irqc->lock);
+
+ return 0;
+}
+
static struct irq_chip intc_dev = {
.name = "StarFive JHB100 INTC",
.irq_unmask = starfive_intc_unmask,
.irq_mask = starfive_intc_mask,
+ .irq_ack = starfive_intc_ack,
+ .irq_set_type = starfive_intc_set_type,
};

static int starfive_intc_map(struct irq_domain *d, unsigned int irq,
--
2.25.1