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Fri, 10 Apr 2026 09:01:19 +0000 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Philipp Zabel Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Ley Foon Tan , Changhuang Liang Subject: [PATCH v1 5/5] irqchip: starfive: Implement irq_set_type and irq_ack hooks Date: Fri, 10 Apr 2026 02:01:06 -0700 Message-Id: <20260410090106.622781-6-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260410090106.622781-1-changhuang.liang@starfivetech.com> References: <20260410090106.622781-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: NT0PR01CA0017.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::6) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1218:EE_ X-MS-Office365-Filtering-Correlation-Id: 392e1857-7885-4c6d-6862-08de96dfbb0e X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|52116014|376014|1800799024|366016|56012099003|38350700014|22082099003|18002099003; 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Also add irq_ack hook as required by handle_edge_irq. Signed-off-by: Changhuang Liang --- drivers/irqchip/irq-starfive-jhb100-intc.c | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/irqchip/irq-starfive-jhb100-intc.c b/drivers/irqchip/irq-starfive-jhb100-intc.c index d5ecbb603a58..d34f960b0770 100644 --- a/drivers/irqchip/irq-starfive-jhb100-intc.c +++ b/drivers/irqchip/irq-starfive-jhb100-intc.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -18,12 +19,20 @@ #include #include +#define STARFIVE_INTC_SRC_TYPE(n) (0x04 + ((n) * 0x20)) #define STARFIVE_INTC_SRC_CLEAR(n) (0x10 + ((n) * 0x20)) #define STARFIVE_INTC_SRC_MASK(n) (0x14 + ((n) * 0x20)) #define STARFIVE_INTC_SRC_INT(n) (0x1c + ((n) * 0x20)) +#define STARFIVE_INTC_TRIGGER_MASK 0x3 +#define STARFIVE_INTC_TRIGGER_HIGH 0 +#define STARFIVE_INTC_TRIGGER_LOW 1 +#define STARFIVE_INTC_TRIGGER_POSEDGE 2 +#define STARFIVE_INTC_TRIGGER_NEGEDGE 3 + #define STARFIVE_INTC_NUM 2 #define STARFIVE_INTC_SRC_IRQ_NUM 32 +#define STARFIVE_INTC_TYPE_NUM 16 struct starfive_irq_chip { void __iomem *base; @@ -31,6 +40,17 @@ struct starfive_irq_chip { raw_spinlock_t lock; }; +static void starfive_intc_mod(struct starfive_irq_chip *irqc, u32 reg, + u32 mask, u32 data) +{ + u32 value; + + value = ioread32(irqc->base + reg) & ~mask; + data &= mask; + data |= value; + iowrite32(data, irqc->base + reg); +} + static void starfive_intc_bit_set(struct starfive_irq_chip *irqc, u32 reg, u32 bit_mask) { @@ -77,10 +97,62 @@ static void starfive_intc_mask(struct irq_data *d) raw_spin_unlock(&irqc->lock); } +static void starfive_intc_ack(struct irq_data *d) +{ + /* for handle_edge_irq, nothing to do */ +} + +static int starfive_intc_set_type(struct irq_data *d, unsigned int type) +{ + struct starfive_irq_chip *irqc = irq_data_get_irq_chip_data(d); + u32 i, bitpos, ty_pos, ty_shift, tmp; + + i = d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM; + bitpos = d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM; + ty_pos = bitpos / STARFIVE_INTC_TYPE_NUM; + ty_shift = (bitpos % STARFIVE_INTC_TYPE_NUM) * 2; + + switch (type) { + case IRQF_TRIGGER_LOW: + tmp = STARFIVE_INTC_TRIGGER_LOW << ty_shift; + irq_set_handler_locked(d, handle_level_irq); + break; + case IRQF_TRIGGER_HIGH: + tmp = STARFIVE_INTC_TRIGGER_HIGH << ty_shift; + irq_set_handler_locked(d, handle_level_irq); + break; + case IRQF_TRIGGER_FALLING: + tmp = STARFIVE_INTC_TRIGGER_NEGEDGE << ty_shift; + irq_set_handler_locked(d, handle_edge_irq); + break; + case IRQF_TRIGGER_RISING: + tmp = STARFIVE_INTC_TRIGGER_POSEDGE << ty_shift; + irq_set_handler_locked(d, handle_edge_irq); + break; + default: + return -EINVAL; + } + + raw_spin_lock(&irqc->lock); + + starfive_intc_mod(irqc, STARFIVE_INTC_SRC_TYPE(i) + 4 * ty_pos, + STARFIVE_INTC_TRIGGER_MASK << ty_shift, tmp); + + /* Once the type is updated, clear interrupt can help to reset the type value */ + starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(bitpos)); + starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(bitpos)); + + raw_spin_unlock(&irqc->lock); + + return 0; +} + static struct irq_chip intc_dev = { .name = "StarFive JHB100 INTC", .irq_unmask = starfive_intc_unmask, .irq_mask = starfive_intc_mask, + .irq_ack = starfive_intc_ack, + .irq_set_type = starfive_intc_set_type, }; static int starfive_intc_map(struct irq_domain *d, unsigned int irq, -- 2.25.1