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Fri, 10 Apr 2026 06:00:00 -0500 Received: from a0512632.dhcp.ti.com (a0512632.dhcp.ti.com [172.24.233.20]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 63AAxtgt076591; Fri, 10 Apr 2026 05:59:56 -0500 From: Swamil Jain To: , , , , , , , , , , CC: , , , , , Subject: [PATCH v3] dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints Date: Fri, 10 Apr 2026 16:29:55 +0530 Message-ID: <20260410105955.843868-1-s-jain1@ti.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCBF:EE_|MW4PR10MB5678:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e994545-fc57-49bc-e7dd-08de96f05032 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|7416014|18002099003|921020|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pWr1c16momkvhKmQ/bzTs//s6UqngclQRR6nPBHW2BbqENixg98hbve4zQl1OrcEFk+glKeQB7fGB0yTCLPbinigfv4J9IHrB0AV0bXyoCkA61G+yU607dicGmBJYxcOTJzoHHEMNV/EhiOoIhxiE9crRHqPJ7FH/s42viYcCsF0CIquAUn8kIGEk0U6ODHxiUW2E05Nv1bANAdjHEQwzG/clTnqBtKfUBGh2XJcaPhFU3WupNCIUkTUNGARHktG9wOgX2kjGg15mcF8691g7xZw/7YVrss1/KrdwQLo3tdgLqc+qJO8PAD3IBPI3S39IK3Sr4N5oypxwCGMNF9tWilek4FO2fkWN2Db1jp2ms15OR/nbQaqEeJvgwbiO+zGRgMnQLlWoSilChQoft6STWHiwiM91c292+G9UUakBn4CgThe5ILE0tNpfHMgtu/m X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2026 11:00:01.4112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e994545-fc57-49bc-e7dd-08de96f05032 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCBF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR10MB5678 The AM62L DSS [1] support incorrectly used the same register and clock constraints as AM65x, but AM62L has a single video port Fix this by adding conditional constraints that properly define the register regions and clocks for AM62L DSS (single video port) versus other AM65x variants (dual video port). [1]: Section 12.7 (Display Subsystem and Peripherals) Link : https://www.ti.com/lit/pdf/sprujb4 Fixes: cb8d4323302c ("dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS") Cc: stable@vger.kernel.org Signed-off-by: Swamil Jain --- Validated the changes with some examples: https://gist.github.com/swamiljain/79f30568c9ece89f5a20218f52647486 Changelog: v2->v3: - Reduce redundancy and use constraints suggested by maintainers - Remove blank line between the tags Link to v2: https://lore.kernel.org/all/20260129150601.185882-1-s-jain1@ti.com/ v1->v2: - Remove oneOf from top level constraints, it makes bindings redundant - Remove minItems from top level constraints - "dma-coherent" property shouldn't be changed in v1 itself - Add description for reg-names, clock and clock-names - Add constraints specific to AM62L and for other SoCs within allOf check Link to v1: https://lore.kernel.org/all/20251224133150.2266524-1-s-jain1@ti.com/ --- .../bindings/display/ti/ti,am65x-dss.yaml | 66 ++++++++++++++----- 1 file changed, 48 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 38fcee91211e..d8a05bf62c2f 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -36,34 +36,50 @@ properties: reg: description: Addresses to each DSS memory region described in the SoC's TRM. - items: - - description: common DSS register area - - description: VIDL1 light video plane - - description: VID video plane - - description: OVR1 overlay manager for vp1 - - description: OVR2 overlay manager for vp2 - - description: VP1 video port 1 - - description: VP2 video port 2 - - description: common1 DSS register area + oneOf: + - items: + - description: common DSS register area + - description: VIDL1 light video plane + - description: VID video plane + - description: OVR1 overlay manager for vp1 + - description: OVR2 overlay manager for vp2 + - description: VP1 video port 1 + - description: VP2 video port 2 + - description: common1 DSS register area + - items: + - description: common DSS register area + - description: VIDL1 light video plane + - description: OVR1 overlay manager for vp1 + - description: VP1 video port 1 + - description: common1 DSS register area reg-names: - items: - - const: common - - const: vidl1 - - const: vid - - const: ovr1 - - const: ovr2 - - const: vp1 - - const: vp2 - - const: common1 + oneOf: + - items: + - const: common + - const: vidl1 + - const: vid + - const: ovr1 + - const: ovr2 + - const: vp1 + - const: vp2 + - const: common1 + - items: + - const: common + - const: vidl1 + - const: ovr1 + - const: vp1 + - const: common1 clocks: + minItems: 2 items: - description: fck DSS functional clock - description: vp1 Video Port 1 pixel clock - description: vp2 Video Port 2 pixel clock clock-names: + minItems: 2 items: - const: fck - const: vp1 @@ -179,6 +195,20 @@ allOf: ports: properties: port@1: false + clock-names: + maxItems: 2 + clocks: + maxItems: 2 + reg: + maxItems: 5 + else: + properties: + clock-names: + minItems: 3 + clocks: + minItems: 3 + reg: + minItems: 8 - if: properties: