From: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
To: Thomas Gleixner <tglx@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: cros-qcom-dts-watchers@chromium.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Subject: [PATCH 05/35] irqchip/qcom-pdc: Add PDC_VERSION() macro to describe version register fields
Date: Sat, 11 Apr 2026 00:10:42 +0530 [thread overview]
Message-ID: <20260410184124.1068210-6-mukesh.ojha@oss.qualcomm.com> (raw)
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC hardware version register encodes major, minor and step fields
in byte-sized fields at bits [23:16], [15:8] and [7:0] respectively.
The existing PDC_VERSION_3_2 constant was a bare magic number (0x30200)
with no indication of this encoding.
Add GENMASK-based field definitions for each sub-field and a
PDC_VERSION(maj, min, step) constructor macro using FIELD_PREP, making
the encoding self-documenting. Replace the magic constant with
PDC_VERSION(3, 2, 0).
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
drivers/irqchip/qcom-pdc.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index 734576cdce0c..5e1553334103 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -3,6 +3,7 @@
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
*/
+#include <linux/bitfield.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
@@ -34,9 +35,16 @@
#define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0)
#define PDC_VERSION_REG 0x1000
+#define PDC_VERSION_MAJOR GENMASK(23, 16)
+#define PDC_VERSION_MINOR GENMASK(15, 8)
+#define PDC_VERSION_STEP GENMASK(7, 0)
+#define PDC_VERSION(maj, min, step) \
+ (FIELD_PREP(PDC_VERSION_MAJOR, (maj)) | \
+ FIELD_PREP(PDC_VERSION_MINOR, (min)) | \
+ FIELD_PREP(PDC_VERSION_STEP, (step)))
/* Notable PDC versions */
-#define PDC_VERSION_3_2 0x30200
+#define PDC_VERSION_3_2 PDC_VERSION(3, 2, 0)
struct pdc_pin_region {
u32 pin_base;
--
2.53.0
next prev parent reply other threads:[~2026-04-10 18:42 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-10 18:40 [PATCH 00/35] irqchip/qcom-pdc: Clean up register mapping and DT descriptions Mukesh Ojha
2026-04-10 18:40 ` [PATCH 01/35] dt-bindings: qcom,pdc: Tighten reg to single APSS DRV region Mukesh Ojha
2026-04-10 18:40 ` [PATCH 02/35] irqchip/qcom-pdc: Split __pdc_enable_intr() into per-version helpers Mukesh Ojha
2026-04-10 18:40 ` [PATCH 03/35] irqchip/qcom-pdc: Tighten ioremap clamp to single DRV region size Mukesh Ojha
2026-04-10 18:40 ` [PATCH 04/35] irqchip/qcom-pdc: Replace pdc_version global with a function pointer Mukesh Ojha
2026-04-11 2:43 ` Bjorn Andersson
2026-04-10 18:40 ` Mukesh Ojha [this message]
2026-04-10 18:40 ` [PATCH 06/35] irqchip/qcom-pdc: Use FIELD_GET() to extract bank index and bit position Mukesh Ojha
2026-04-10 18:40 ` [PATCH 07/35] arm64: dts: qcom: sdm845: Fix PDC reg size to single APSS DRV region Mukesh Ojha
2026-04-10 18:40 ` [PATCH 08/35] arm64: dts: qcom: sdm670: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 09/35] arm64: dts: qcom: sc7180: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 10/35] arm64: dts: qcom: sc7280: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 11/35] arm64: dts: qcom: sc8180x: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 12/35] arm64: dts: qcom: sm8150: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 13/35] arm64: dts: qcom: sc8280xp: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 14/35] arm64: dts: qcom: sm8250: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 15/35] arm64: dts: qcom: sm8350: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 16/35] arm64: dts: qcom: sm8450: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 17/35] arm64: dts: qcom: sm8550: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 18/35] arm64: dts: qcom: sm8650: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 19/35] arm64: dts: qcom: sm4450: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 20/35] arm64: dts: qcom: x1e80100: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 21/35] arm64: dts: qcom: sm6350: " Mukesh Ojha
2026-04-10 18:40 ` [PATCH 22/35] arm64: dts: qcom: sar2130p: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 23/35] arm64: dts: qcom: qcs615: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 24/35] arm64: dts: qcom: qcs8300: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 25/35] arm64: dts: qcom: sa8775p: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 26/35] arm64: dts: qcom: sdx75: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 27/35] arm64: dts: qcom: milos: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 28/35] arm64: dts: qcom: qdu1000: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 29/35] arm64: dts: qcom: kaanapali: Drop unused second PDC reg entry Mukesh Ojha
2026-04-10 18:41 ` [PATCH 30/35] arm64: dts: qcom: lemans: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 31/35] arm64: dts: qcom: milos: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 32/35] arm64: dts: qcom: monaco: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 33/35] arm64: dts: qcom: sc8280xp: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 34/35] arm64: dts: qcom: sdx75: " Mukesh Ojha
2026-04-10 18:41 ` [PATCH 35/35] arm64: dts: qcom: talos: " Mukesh Ojha
2026-04-11 2:48 ` [PATCH 00/35] irqchip/qcom-pdc: Clean up register mapping and DT descriptions Bjorn Andersson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260410184124.1068210-6-mukesh.ojha@oss.qualcomm.com \
--to=mukesh.ojha@oss.qualcomm.com \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=cros-qcom-dts-watchers@chromium.org \
--cc=devicetree@vger.kernel.org \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh@kernel.org \
--cc=tglx@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox