From: Krzysztof Kozlowski <krzk@kernel.org>
To: Swamil Jain <s-jain1@ti.com>
Cc: jyri.sarha@iki.fi, tomi.valkeinen@ideasonboard.com,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
devarsht@ti.com, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
praneeth@ti.com, vigneshr@ti.com
Subject: Re: [PATCH v3] dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints
Date: Sat, 11 Apr 2026 16:07:53 +0200 [thread overview]
Message-ID: <20260411-resilient-tireless-centipede-cd6fef@quoll> (raw)
In-Reply-To: <20260410105955.843868-1-s-jain1@ti.com>
On Fri, Apr 10, 2026 at 04:29:55PM +0530, Swamil Jain wrote:
> clocks:
> + minItems: 2
> items:
> - description: fck DSS functional clock
> - description: vp1 Video Port 1 pixel clock
> - description: vp2 Video Port 2 pixel clock
>
> clock-names:
> + minItems: 2
> items:
> - const: fck
> - const: vp1
> @@ -179,6 +195,20 @@ allOf:
> ports:
> properties:
> port@1: false
> + clock-names:
> + maxItems: 2
> + clocks:
> + maxItems: 2
> + reg:
> + maxItems: 5
Also constrain for reg-names,
> + else:
> + properties:
> + clock-names:
> + minItems: 3
> + clocks:
> + minItems: 3
> + reg:
> + minItems: 8
Same here, please.
And if you are sending new version: they should be listed in the same
order as in top-level properties, so reg, reg-names, clocks and
clock-names. (juging by the diff)
Best regards,
Krzysztof
prev parent reply other threads:[~2026-04-11 14:07 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-10 10:59 [PATCH v3] dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints Swamil Jain
2026-04-11 14:07 ` Krzysztof Kozlowski [this message]
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