From: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
To: Neil Armstrong <neil.armstrong@linaro.org>,
Jessica Zhang <jesszhan0024@gmail.com>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Cong Yang <yangcong5@huaqin.corp-partner.google.com>,
Ondrej Jirman <megi@xff.cz>,
Javier Martinez Canillas <javierm@redhat.com>,
Jagan Teki <jagan@edgeble.ai>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
Riccardo Mereu <r.mereu@arduino.cc>
Subject: [PATCH v2 15/21] drm/panel: jadard-jd9365da-h3: support Waveshare WXGA DSI panels
Date: Sat, 11 Apr 2026 15:10:35 +0300 [thread overview]
Message-ID: <20260411-waveshare-dsi-touch-v2-15-75cdbeac5156@oss.qualcomm.com> (raw)
In-Reply-To: <20260411-waveshare-dsi-touch-v2-0-75cdbeac5156@oss.qualcomm.com>
Add configuration for several Waveshare 8.0" and 10.1" WXGA DSI panels
using JD9365 controller
Tested-by: Riccardo Mereu <r.mereu@arduino.cc>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 568 +++++++++++++++++++++++
1 file changed, 568 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index aacb8968cd01..49c47f2bfbb9 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -2067,6 +2067,566 @@ static const struct jadard_panel_desc waveshare_4_0_inch_c_desc = {
MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
};
+static int waveshare_8_0_a_init(struct jadard *jadard)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ jadard_enable_standard_cmds(&dsi_ctx);
+
+ jd9365da_switch_page(&dsi_ctx, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7e);
+ else
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xb7);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xb7);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x70);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xa9);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x78);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x63);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x54);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x23);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x62);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10);
+
+ jd9365da_switch_page(&dsi_ctx, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x56);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xf8);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xd5);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x7b);
+
+ jd9365da_switch_page(&dsi_ctx, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x2a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59);
+ if (jadard->dsi->lanes != 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);
+ }
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+ msleep(120);
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ msleep(60);
+
+ return 0;
+}
+
+static const struct drm_display_mode waveshare_8_0_a_mode = {
+ .clock = (800 + 40 + 20 + 20) * (1280 + 30 + 12 + 4) * 60 / 1000,
+
+ .hdisplay = 800,
+ .hsync_start = 800 + 40,
+ .hsync_end = 800 + 40 + 20,
+ .htotal = 800 + 40 + 20 + 20,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 30,
+ .vsync_end = 1280 + 30 + 12,
+ .vtotal = 1280 + 30 + 12 + 4,
+
+ .width_mm = 107,
+ .height_mm = 172,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct jadard_panel_desc waveshare_8_0_inch_a_desc = {
+ .mode_4ln = &waveshare_8_0_a_mode,
+ .mode_2ln = &waveshare_8_0_a_mode,
+ .format = MIPI_DSI_FMT_RGB888,
+ .init = waveshare_8_0_a_init,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+};
+
+static const struct drm_display_mode waveshare_10_1_a_mode = {
+ .clock = (800 + 40 + 20 + 20) * (1280 + 20 + 20 + 4) * 60 / 1000,
+
+ .hdisplay = 800,
+ .hsync_start = 800 + 40,
+ .hsync_end = 800 + 40 + 20,
+ .htotal = 800 + 40 + 20 + 20,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 20,
+ .vsync_end = 1280 + 20 + 20,
+ .vtotal = 1280 + 20 + 20 + 4,
+
+ .width_mm = 135,
+ .height_mm = 216,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static int waveshare_10_1_a_init(struct jadard *jadard)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ jadard_enable_standard_cmds(&dsi_ctx);
+
+ jd9365da_switch_page(&dsi_ctx, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3b);
+ else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x38);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x38);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xaf);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xaf);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0d);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x6b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x5c);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x6a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x5b);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4f);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2b);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2a);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x5a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0f);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x59);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x3a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x26);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5c);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5b);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4f);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2b);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2a);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x63);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x62);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x52);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x5a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0f);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x59);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x3a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x26);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);
+
+ jd9365da_switch_page(&dsi_ctx, 0x02);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x37);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x42);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x42);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x77);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49);
+ if (jadard->dsi->lanes == 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37);
+ } else {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x5e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x77);
+ }
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x48);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f);
+ else
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x16);
+ else
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x34);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1d);
+ else
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xdd);
+ if (jadard->dsi->lanes == 4)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3f);
+ else
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x14);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x82);
+
+ jd9365da_switch_page(&dsi_ctx, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);
+ if (jadard->dsi->lanes != 4) {
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);
+ }
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe7, 0x0c);
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+ msleep(120);
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ msleep(60);
+
+ return dsi_ctx.accum_err;
+}
+
+static const struct jadard_panel_desc waveshare_10_1_inch_a_desc = {
+ .mode_4ln = &waveshare_10_1_a_mode,
+ .mode_2ln = &waveshare_10_1_a_mode,
+ .format = MIPI_DSI_FMT_RGB888,
+ .init = waveshare_10_1_a_init,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+};
+
static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
{
struct device *dev = &dsi->dev;
@@ -2184,6 +2744,14 @@ static const struct of_device_id jadard_of_match[] = {
.compatible = "waveshare,4.0-dsi-touch-c",
.data = &waveshare_4_0_inch_c_desc
},
+ {
+ .compatible = "waveshare,8.0-dsi-touch-a",
+ .data = &waveshare_8_0_inch_a_desc
+ },
+ {
+ .compatible = "waveshare,10.1-dsi-touch-a",
+ .data = &waveshare_10_1_inch_a_desc
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jadard_of_match);
--
2.47.3
next prev parent reply other threads:[~2026-04-11 12:11 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-11 12:10 [PATCH v2 00/21] drm/panel: support Waveshare DSI TOUCH kits Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 01/21] dt-bindings: display/panel: himax,hx83102: describe Waveshare panel Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 02/21] dt-bindings: display/panel: himax,hx8394: " Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 03/21] dt-bindings: display/panel: jadard,jd9365da-h3: " Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 04/21] dt-bindings: display/panel: ilitek,ili9881c: " Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 05/21] dt-bindings: dipslay/panel: describe panels using Focaltech OTA7290B Dmitry Baryshkov
2026-04-11 14:02 ` Rob Herring (Arm)
2026-04-11 12:10 ` [PATCH v2 06/21] drm/of: add helper to count data-lanes on a remote endpoint Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 07/21] drm/panel: himax-hx83102: support Waveshare 12.3" DSI panel Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 08/21] drm/panel: himax-hx8394: set prepare_prev_first Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 09/21] drm/panel: himax-hx8394: simplify hx8394_enable() Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 10/21] drm/panel: himax-hx8394: support Waveshare DSI panels Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 11/21] drm/panel: jadard-jd9365da-h3: use drm_connector_helper_get_modes_fixed Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 12/21] drm/panel: jadard-jd9365da-h3: support variable DSI configuration Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 13/21] drm/panel: jadard-jd9365da-h3: set prepare_prev_first Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 14/21] drm/panel: jadard-jd9365da-h3: support Waveshare round DSI panels Dmitry Baryshkov
2026-04-11 12:10 ` Dmitry Baryshkov [this message]
2026-04-11 12:10 ` [PATCH v2 16/21] drm/panel: jadard-jd9365da-h3: support Waveshare 720p " Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 17/21] drm/panel: ilitek-ili9881c: support Waveshare 7.0" DSI panel Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 18/21] drm/panel: add devm_drm_panel_add() helper Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 19/21] drm/panel: add driver for Waveshare 8.8" DSI TOUCH-A panel Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 20/21] dt-bindings: gpio: describe Waveshare GPIO controller Dmitry Baryshkov
2026-04-11 12:10 ` [PATCH v2 21/21] gpio: add GPIO controller found on Waveshare DSI TOUCH panels Dmitry Baryshkov
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