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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?YbdJ3uOVUGjGPVGl+4QswiCyV4xvQMXGL8x75D6Lgis8FmRg1C0fNp6wPhgu?= =?us-ascii?Q?9OTSFy5KMgcHj5lFsMppxrsEbJve/f4MwWSyill1KVm/bLCPgnbiRNPvuIxU?= =?us-ascii?Q?Wazm0EpvKTxbelNrPI6ZKTmGAubc2ebzZh2VaeljQSO9ulTAMl0QblYzV9UV?= =?us-ascii?Q?1CDAeRASGdI4D4+rZoBvLXyWLzDvocFqUB64s7MKKTx533Hqw0rtVoVy/vbB?= =?us-ascii?Q?Ik8mOYVmS00EDGXJmX5KNVJClStmyD/NNQzwENVyfn5wkKxddQr2vVBwA59j?= =?us-ascii?Q?OGU6ACKalXuIVlXAAwCa+4XJTPyGhFpvgdQbvFYjuLRL37wziKe0qKzJykjo?= =?us-ascii?Q?5XV9v7x2rcNmNnaunsI0yx6lqbtF1tY/xfhKbVXJwzVNIz6GKb3l+VGxH6tW?= =?us-ascii?Q?0FMbqENKp4gRk5cTmhfWba3+p3MOS0LV97gPhYvF4dyTch0F5LXmazUVyuT6?= =?us-ascii?Q?P57egLdgw9zZqFDscLH6saDBDpllZvluYgdAhC1Qr60cBWLtPA2/ykxftGf2?= =?us-ascii?Q?azW92ED3tlhftVsfEeRg3nKhwv9SnqQChgNEpTohl9v1S5qItdyYfytNbkue?= =?us-ascii?Q?YXj1gVLnkW6HBNnto/k8rJIfQGpG6Zu3BCqKefF0mcNMug4UatiwBnTo6z4N?= =?us-ascii?Q?Nguigmqj/BWLBmnnrTmsTmTgtN7+N7ZS/4E3WdqgSgGjluMWBWKXsDFkpErC?= =?us-ascii?Q?zYsQuqDRWsuX7t8L/m77sjI1ZVbdMXIlrpYtjdhCRFL8IN4cbK/QVRCDIzNS?= =?us-ascii?Q?RFgYeqcPVJnpX2oPuXziud+r5U1Hqtu0tWMx9KU4J04KuZVcXaqP1J1hPzWX?= =?us-ascii?Q?SeqOML3726SnRwTt1Vs2dStX7JH8hIy1mYO6oMAbIYBLnDHvyjoPvrqWG+2D?= =?us-ascii?Q?NIevjMJDnZputVWN5/zWKFGy5VIxkwATblsv9S2S1EhsYLSjKOrYIakVC4Fa?= =?us-ascii?Q?tX1TmstTHEc7v7jD7LXUJVQ5T1wSuvO7YoMAS9ui3cDBXMaJZZwDRCunsg8S?= =?us-ascii?Q?ZIMUGA3XygNOBp0VFWR33vr2vXU+cYAig1abBu34eicViF8wQLCf4RhWKe/n?= =?us-ascii?Q?OtNEixRYC29fffk11aBhlB2zREYXZaFYarz6onQl/n1GImLys89QxOBT9mUo?= =?us-ascii?Q?WNx7A6atD9WyVQXXbPdeBQ+5n4MjiPwpautLJwugPrjH+WQ24VaD+EbI8Lb7?= =?us-ascii?Q?+fPlWkPm6fFRAvU2Y+OUwHCFXRBaUDVxzsGTbB6Blkgjx7AGWlLzLhLoaOIZ?= =?us-ascii?Q?kyeTjqZEsDbDoxM4MMvQJPI7/TTBHAHJJhvR/3fHGbIKzo64+e64VM/OdKnb?= =?us-ascii?Q?768lYHaXYEtYJElV/cG6E68UQls27Ob9xqrNFgbpjfpTosjhUW54QKISC2Ke?= =?us-ascii?Q?m6uSM55UwAyOx6LsqejRSvbhIwfivBAYLhndAF0F593BIEn1yWgguFxfotbz?= =?us-ascii?Q?Z4HlV9jRxE4t4kXHSWuEAQGojqr1EcLfBzgRT988jL9Dotk9LDCfrfud3U58?= =?us-ascii?Q?/5Pc8ozKNMKjLzeGH0QjTkjP6uxb/2lHc8CbIc1FsDldpe6hFI292o6M19hx?= =?us-ascii?Q?PWnIeQgEaiXtU69bsmFyUvFN/rdU54fe4ExahDC1CDqpyjSyncSnG+NTS9Dq?= =?us-ascii?Q?VrwIywQPUUu7fYzBf0/+DDXfSWNcKCQS3h0F58o3L5tHP88vDobntlKXdMo8?= =?us-ascii?Q?YNwZWBIpDn9F/Lx/iesYLczQ7KxvWQywbp/a5YjqghVH4mM1?= X-OriginatorOrg: axon.com X-MS-Exchange-CrossTenant-Network-Message-Id: e3a91da3-29d8-400b-19f2-08de993c71cb X-MS-Exchange-CrossTenant-AuthSource: SA2PR10MB4524.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 09:10:02.1785 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b575368d-7461-447d-a9a4-f90f22962981 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: v3I1zG0jFZL3wbNS085x4+s6901jk2Svqu1pWQbJhpVwkTLedj5Q097ZdjxUpXNkgSx8fYv2wkkVjILZ3fZmdA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR10MB6367 On Mon, Apr 13, 2026 at 04:39:55AM +0300, Dmitry Baryshkov wrote: > On Thu, Apr 09, 2026 at 04:26:57PM +0100, Joe Sandom wrote: > > The RB5gen2 is an embedded development platform for the > > QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550). > > > > This change implements the main board, the vision mezzanine > > will be supported in a follow up patch. > > > > The main board has the following features: > > - Qualcomm Dragonwing QCS8550 SoC > > - Adreno GPU 740 > > - Spectra ISP > > - Adreno VPU 8550 > > - Adreno DPU 1295 > > - 1 x 1GbE Ethernet (USB Ethernet) > > - WIFI 7 + Bluetooth 5.4 > > - 1 x USB 2.0 Micro B (Debug) > > - 1 x USB 3.0 Type C (ADB, DP out) > > - 2 x USB 3.0 Type A > > - 1 x HDMI 1.4 Type A > > - 1 x DP 1.4 Type C > > - 2 x WSA8845 Speaker amplifiers > > - 2 x Speaker connectors > > - 1 x On Board PDM MIC > > - Accelerometer + Gyro Sensor > > - 96Boards compatible low-speed and high-speed connectors [1] > > - 7 x LED indicators (4 user, 2 radio, 1 power) > > - Buttons for power, volume up/down, force USB boot > > - 3 x Dip switches > > > > On-Board PMICs: > > - PMK8550 2.1 > > - PM8550 2.0 > > - PM8550VS 2.0 x4 > > - PM8550VE 2.0 > > - PM8550B 2.0 > > - PMR735D 2.0 > > - PM8010 1.1 x2 > > > > Product Page: [2] > > > > [1] https://urldefense.com/v3/__https://www.96boards.org/specifications/__;!!K76kBA!3gMyDZ3RqJTInuD9UAhneyD_Ga1OTDOm5CbLp15KXHLPV8aflL7_S_i89xs_S_dJ2SHGHnEEyMD5zZMi7iWLAuaVhZPXvg$ > > [2] https://urldefense.com/v3/__https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit__;!!K76kBA!3gMyDZ3RqJTInuD9UAhneyD_Ga1OTDOm5CbLp15KXHLPV8aflL7_S_i89xs_S_dJ2SHGHnEEyMD5zZMi7iWLAuaUXzBHLA$ > > > > The default msi-map from sm8550.dtsi is deleted for both pcie0 and > > pcie1. The QPS615 PCIe switch on each port exposes more than two > > devices (1 USP + 3 DSPs), but Gunyah currently limits ITS device > > mappings to two per root complex to save memory. With msi-map > > present, the ITS MAPD command times out. > > > > Deleting msi-map causes the DWC controller to fall back to its > > internal iMSI-RX module, which handles MSIs without this limitation. > > > > Signed-off-by: Joe Sandom > > --- > > arch/arm64/boot/dts/qcom/Makefile | 1 + > > arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 1573 ++++++++++++++++++++++++++ > > 2 files changed, 1574 insertions(+) > > > > + > > + lt9611_1v2: lt9611-regulator-1v2 { > > I think that comes from the RB5 or something similar. Could you please > rename the nodes to follow the pattern used by other regulators > (regulator-foo-bar) and place these supplies accordingly. > Good point, will amend for v4. > > + compatible = "regulator-fixed"; > > + regulator-name = "LT9611_1V2"; > > + > > + regulator-min-microvolt = <1200000>; > > + regulator-max-microvolt = <1200000>; > > + > > + vin-supply = <&vreg_l14b_3p2>; > > + }; > > + > > + lt9611_3v3: lt9611-regulator-3v3 { > > + compatible = "regulator-fixed"; > > + regulator-name = "LT9611_3V3"; > > + > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + > > + vin-supply = <&vreg_l14b_3p2>; > > + }; > > + > > + pmic-glink { > > + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + connector@0 { > > + compatible = "usb-c-connector"; > > + reg = <0>; > > + power-role = "dual"; > > + data-role = "dual"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + > > + pmic_glink_hs_in: endpoint { > > + remote-endpoint = <&usb_1_dwc3_hs>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + > > + pmic_glink_ss_in: endpoint { > > + remote-endpoint = <&redriver_usb_con_ss>; > > + }; > > + }; > > + > > + port@2 { > > + reg = <2>; > > + > > + pmic_glink_sbu_in: endpoint { > > + remote-endpoint = <&redriver_usb_con_sbu>; > > + }; > > + }; > > + }; > > + }; > > + }; > > + > > + pcie_upd_1p05: regulator-pcie-upd-1p05 { > > + compatible = "regulator-fixed"; > > + regulator-name = "PCIE_UPD_1P05"; > > + gpio = <&tlmm 179 GPIO_ACTIVE_HIGH>; > > + vin-supply = <&vdd_ntn_0p9>; > > + regulator-min-microvolt = <1050000>; > > + regulator-max-microvolt = <1050000>; > > + enable-active-high; > > + regulator-enable-ramp-delay = <5000>; > > + pinctrl-0 = <&upd_1p05_en>; > > + pinctrl-names = "default"; > > + }; > > + > > + pcie_upd_3p3: regulator-pcie-upd-3p3 { > > + compatible = "regulator-fixed"; > > + regulator-name = "PCIE_UPD_3P3"; > > + gpio = <&tlmm 13 GPIO_ACTIVE_HIGH>; > > + vin-supply = <&pcie_upd_1p05>; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + enable-active-high; > > + regulator-enable-ramp-delay = <10000>; > > + pinctrl-0 = <&upd_3p3_en>; > > + pinctrl-names = "default"; > > + }; > > + > > + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { > > + compatible = "regulator-fixed"; > > + regulator-name = "VDD_NTN_0P9"; > > + vin-supply = <&vdd_ntn_1p8>; > > + regulator-min-microvolt = <899400>; > > + regulator-max-microvolt = <899400>; > > + regulator-enable-ramp-delay = <4300>; > > + }; > > + > > + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { > > + compatible = "regulator-fixed"; > > + regulator-name = "VDD_NTN_1P8"; > > + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + enable-active-high; > > + pinctrl-0 = <&ntn0_en>; > > + pinctrl-names = "default"; > > + regulator-enable-ramp-delay = <10000>; > > + }; > > + > > + vdd_ntn1_0p9: regulator-vdd-ntn1-0p9 { > > + compatible = "regulator-fixed"; > > + regulator-name = "VDD_NTN1_0P9"; > > + vin-supply = <&vdd_ntn1_1p8>; > > + regulator-min-microvolt = <899400>; > > + regulator-max-microvolt = <899400>; > > + regulator-enable-ramp-delay = <4300>; > > + }; > > + > > + vdd_ntn1_1p8: regulator-vdd-ntn1-1p8 { > > + compatible = "regulator-fixed"; > > + regulator-name = "VDD_NTN1_1P8"; > > + gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + enable-active-high; > > + pinctrl-0 = <&ntn1_en>; > > + pinctrl-names = "default"; > > + regulator-enable-ramp-delay = <10000>; > > + }; > > + > > + vph_pwr: regulator-vph-pwr { > > + compatible = "regulator-fixed"; > > + regulator-name = "vph_pwr"; > > + regulator-min-microvolt = <3700000>; > > + regulator-max-microvolt = <3700000>; > > + > > + regulator-always-on; > > + regulator-boot-on; > > + }; > > + > > + sound { > > + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard"; > > + model = "QCS8550-RB5Gen2"; > > + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", > > + "SpkrRight IN", "WSA_SPK2 OUT", > > + "VA DMIC0", "vdd-micb", > > + "VA DMIC1", "vdd-micb"; > > + > > + wsa-dai-link { > > + link-name = "WSA Playback"; > > + > > + cpu { > > + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; > > + }; > > + > > + codec { > > codec < cpu Ack. Will amend for v4. > > > + sound-dai = <&left_spkr>, <&right_spkr>, > > + <&swr0 0>, <&lpass_wsamacro 0>; > > + }; > > + > > + platform { > > + sound-dai = <&q6apm>; > > + }; > > + }; > > + > > + va-dai-link { > > + link-name = "VA Capture"; > > + > > + cpu { > > + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; > > + }; > > + > > + codec { > > + sound-dai = <&lpass_vamacro 0>; > > + }; > > + > > + platform { > > + sound-dai = <&q6apm>; > > + }; > > + }; > > + }; > > + > > + > > +&i2c_hub_3_gpio { > > + clock-frequency = <400000>; > > + > > + status = "okay"; > > + > > + lt9611_codec: hdmi-bridge@2b { > > + compatible = "lontium,lt9611uxc"; > > + reg = <0x2b>; > > + > > + interrupts-extended = <&tlmm 40 IRQ_TYPE_EDGE_FALLING>; > > + reset-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; > > + > > + vdd-supply = <<9611_1v2>; > > + vcc-supply = <<9611_3v3>; > > + > > + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; > > pinctrl-0 = <<9611_irq_pin>, <<9611_rst_pin>; > Ack. Also another instance of this for the tc9563. Will amend both for v4. > > > + pinctrl-names = "default"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + > > + lt9611_a: endpoint { > > + remote-endpoint = <&mdss_dsi0_out>; > > + }; > > + }; > > + > > + port@2 { > > + reg = <2>; > > + > > + lt9611_out: endpoint { > > + remote-endpoint = <&hdmi_con>; > > + }; > > + }; > > + }; > > + }; > > +}; > > + > > + > > +&remoteproc_adsp { > > + firmware-name = "qcom/qcs8550/adsp.mbn", > > + "qcom/qcs8550/adsp_dtb.mbn"; > > Sound and GPU firmware is under qcom/sm8550/. Let's don't multiply > entities and keep all firmware in the same subdir (including the IPA > firmware too). > Fair point. Will amend for v4. > > + status = "okay"; > > +}; > > + > > +&remoteproc_cdsp { > > + firmware-name = "qcom/qcs8550/cdsp.mbn", > > + "qcom/qcs8550/cdsp_dtb.mbn"; > > + status = "okay"; > > +}; > > + > > +&remoteproc_mpss { > > + firmware-name = "qcom/qcs8550/modem.mbn", > > + "qcom/qcs8550/modem_dtb.mbn"; > > + status = "okay"; > > +}; > > + > > -- > With best wishes > Dmitry Thanks for your review Dmitry. - Joe