Re: [PATCH v4 1/2] dt-bindings: pwm: dwc: add reset optional

Conor Dooley
2026-04-15T15:09:54Z

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On Wed, Apr 15, 2026 at 05:50:20PM +0800, dongxuyang@eswincomputing.com wrote:
> From: Xuyang Dong <dongxuyang@eswincomputing.com>
>
> The DesignWare PWM includes separate reset signals dedicated to each clock
> domain:
> The presetn signal resets logic in pclk domain.
> The timer_N_resetn signal resets logic in the timer_N_clk domain.
> The resets are active-low.
>
> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>

This commit implies that your hardware differs from existing devices,
I think you should add a device-specific compatible.

> ---
> .../devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
> index 7523a89a1773..a8bbad0360f8 100644
> --- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
> +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
> @@ -43,6 +43,9 @@ properties:
> - const: bus
> - const: timer
>
> + resets:
> + maxItems: 2
> +
> snps,pwm-number:
> $ref: /schemas/types.yaml#/definitions/uint32
> description: The number of PWM channels configured for this instance
> --
> 2.34.1
>

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