From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-10629.protonmail.ch (mail-10629.protonmail.ch [79.135.106.29]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A443027B357 for ; Thu, 16 Apr 2026 11:05:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.29 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776337540; cv=none; b=pTeCmQW9CljRWUKTnvpTzxNZ1U8eVxsNC+HSxEz68PKv/M6hgbbVTvKEvtKN4Af6D5SFspHJwCB2ytOuAonIV9LHGxD4uJqjBbb8JiDkDW1SBMNvAHPesj4n8MWKMnWVc5jVLfJC+q8Vy+CCYdTw5vT9zTl8yMaequdw7j4hvMk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776337540; c=relaxed/simple; bh=Tpnj9uF4ZKfxDszPrsQeXalLh7hFaXn6bvO+xHvviac=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PlnrsbrfQHVPcWLMvEVzMrkPhSkXLZmnG0/MHjxYySP1pQAp2A42soTU4jSclezWAmH6tnE1GTa6hADC0O6trrtu0Hu5t5SEvkkfAUQsAz7Xzu6+GOv+g7JpX0ERgLGx6MlowAEIuGJe4LxhsmzPNVZRIBBiQIqkzJsOY4lhJZc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=hC1FmAhV; arc=none smtp.client-ip=79.135.106.29 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="hC1FmAhV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1776337531; x=1776596731; bh=Tpnj9uF4ZKfxDszPrsQeXalLh7hFaXn6bvO+xHvviac=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=hC1FmAhVsqXmkKPzb4mkqW7j0hbc80e4gqzIDiL0hi6vqzxcNQVwhyQFz7TDW8mDm cIliwQsya0Uwg8/ocW2m5VzfWhCXGqZ4YI8Znx9pywAxx0YZ2Og5aogO5YzzibLsXL tW+frAbZ1q87xA0kmZYXxjgSeLljV6dQyKuRsh8oAXRP+qIjs+bgDoB+rXF+aBwBvJ ffNhsoNFnzyq9Co/9vpqlD141XO45s8hw+w5Y9UN5VfA9OIikpNDBlB3oa89aVKVXJ ZMWiUGLLfmtXragSSCiYy8Ery0YLcIw9SNbQGVyx+B/Y+JnB22w14bq/lBPQ/ghHpt KiDVt9Ic4qPoA== Date: Thu, 16 Apr 2026 11:05:25 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich , Konrad Dybcio Subject: [PATCH RFC v4 4/7] drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC Message-ID: <20260416-adreno-810-v4-4-61676e073f8a@pm.me> In-Reply-To: <20260416-adreno-810-v4-0-61676e073f8a@pm.me> References: <20260416-adreno-810-v4-0-61676e073f8a@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: ecd9393e5246509b7d0156ceb6e17f01f8eaa303 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Platforms without a LLCC (e.g. milos) still need to be able to read and write to the cx_mem region. Previously if LLCC slices were unavailable the cx_misc_mmio mapping was overwritten with ERR_PTR, causing a crash when the GMU later accessed cx_mem. Move the cx_misc_mmio mapping out of a6xx_llc_slices_init() into a6xx_gpu_init() so that cx_mem mapping is independent of LLCC. Reviewed-by: Konrad Dybcio Reviewed-by: Akhil P Oommen Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 ++++++++++++++++---------------= ---- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 4275c1d726b2..533272e11111 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) =09struct msm_gpu *gpu =3D &adreno_gpu->base; =09u32 cntl1_regval =3D 0; =20 -=09if (IS_ERR(a6xx_gpu->cx_misc_mmio)) +=09if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw= _llc_slice)) =09=09return; =20 =09if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) =09struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; =09struct msm_gpu *gpu =3D &adreno_gpu->base; =20 -=09if (IS_ERR(a6xx_gpu->cx_misc_mmio)) +=09if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw= _llc_slice)) =09=09return; =20 =09if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2135,31 +2135,12 @@ static void a6xx_llc_slices_destroy(struct a6xx_gpu= *a6xx_gpu) static void a6xx_llc_slices_init(struct platform_device *pdev, =09=09struct a6xx_gpu *a6xx_gpu, bool is_a7xx) { -=09struct device_node *phandle; - =09/* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ =09if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) =09=09return; =20 -=09/* -=09 * There is a different programming path for A6xx targets with an -=09 * mmu500 attached, so detect if that is the case -=09 */ -=09phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); -=09a6xx_gpu->have_mmu500 =3D (phandle && -=09=09of_device_is_compatible(phandle, "arm,mmu-500")); -=09of_node_put(phandle); - -=09if (is_a7xx || !a6xx_gpu->have_mmu500) -=09=09a6xx_gpu->cx_misc_mmio =3D msm_ioremap(pdev, "cx_mem"); -=09else -=09=09a6xx_gpu->cx_misc_mmio =3D NULL; - =09a6xx_gpu->llc_slice =3D llcc_slice_getd(LLCC_GPU); =09a6xx_gpu->htw_llc_slice =3D llcc_slice_getd(LLCC_GPUHTW); - -=09if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw= _llc_slice)) -=09=09a6xx_gpu->cx_misc_mmio =3D ERR_PTR(-EINVAL); } =20 #define GBIF_CLIENT_HALT_MASK=09=09BIT(0) @@ -2621,6 +2602,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devic= e *dev) =09struct platform_device *pdev =3D priv->gpu_pdev; =09struct adreno_platform_config *config =3D pdev->dev.platform_data; =09const struct adreno_info *info =3D config->info; +=09struct device_node *phandle; =09struct device_node *node; =09struct a6xx_gpu *a6xx_gpu; =09struct adreno_gpu *adreno_gpu; @@ -2657,6 +2639,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devi= ce *dev) =20 =09a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 +=09/* +=09 * There is a different programming path for A6xx targets with an +=09 * mmu500 attached, so detect if that is the case +=09 */ +=09phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); +=09a6xx_gpu->have_mmu500 =3D (phandle && +=09=09of_device_is_compatible(phandle, "arm,mmu-500")); +=09of_node_put(phandle); + +=09if (is_a7xx || !a6xx_gpu->have_mmu500) +=09=09a6xx_gpu->cx_misc_mmio =3D msm_ioremap(pdev, "cx_mem"); +=09else +=09=09a6xx_gpu->cx_misc_mmio =3D NULL; + =09ret =3D a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info); =09if (ret) { =09=09a6xx_llc_slices_destroy(a6xx_gpu); --=20 2.53.0