[PATCH v2 0/5] Add interrupt controller for JHB100 SoC

Changhuang Liang
2026-04-16T07:03:38Z

This patchset adds external interrupt controller driver for the StarFive
JHB100 SoC. It supports up to 64 interrupt sources, and both level and
edge trigger types.

changes since v1:
- irqchip: starfive -> irqchip/starfive

patch 1:
- Update commit title and add Conor's Acked-by tag

patch 3:
- Use __free(kfree) cleanup
- Replace dev_err() with dev_err_probe()
- Replace devm_reset_control_get_optional() + reset_control_deassert()
with devm_reset_control_get_optional_exclusive_deasserted()

patch 4:
- Use guard(raw_spinlock)

patch 5:
- Update starfive_intc_set_type()

v1: https://lore.kernel.org/all/20260410090106.622781-1-changhuang.liang@starfivetech.com/

Changhuang Liang (4):
dt-bindings: interrupt-controller: repurpose binding for unreleased
jh8100 for jhb100
irqchip/starfive: Rename jh8100 to jhb100
irqchip/starfive: Use devm_ interfaces to simplify resource release
irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks

Mason Huo (1):
irqchip/starfive: Increase the interrupt source number up to 64

...00-intc.yaml => starfive,jhb100-intc.yaml} | 20 +-
MAINTAINERS | 6 +-
drivers/irqchip/Kconfig | 6 +-
drivers/irqchip/Makefile | 2 +-
drivers/irqchip/irq-starfive-jh8100-intc.c | 207 --------------
drivers/irqchip/irq-starfive-jhb100-intc.c | 254 ++++++++++++++++++
6 files changed, 265 insertions(+), 230 deletions(-)
rename Documentation/devicetree/bindings/interrupt-controller/{starfive,jh8100-intc.yaml => starfive,jhb100-intc.yaml} (68%)
delete mode 100644 drivers/irqchip/irq-starfive-jh8100-intc.c
create mode 100644 drivers/irqchip/irq-starfive-jhb100-intc.c

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2.25.1