[PATCH v6 04/21] clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks

Tommaso Merciai
2026-04-08T10:38:22Z

Add the CLK_PLLDSI0_DIV7 and CLK_PLLDSI1_DIV7 fixed-factor clocks to
the r9a09g047 SoC clock driver.

These clocks are required to enable LVDS0 and LVDS1 output support.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v5->v6:
- No changes.

v4->v5:
- No changes.

v3->v4:
- No changes.

v2->v3:
- No changes.

v1->v2:
- Collected GUytterhoeven tag.

drivers/clk/renesas/r9a09g047-cpg.c | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 87d5924f7e79..fd9b49c39dac 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -69,6 +69,8 @@ enum clk_ids {
CLK_PLLVDO_GPU,
CLK_PLLETH_DIV4_LPCLK,
CLK_PLLETH_LPCLK,
+ CLK_PLLDSI0_DIV7,
+ CLK_PLLDSI1_DIV7,

/* Module Clocks */
MOD_CLK_BASE,
@@ -196,6 +198,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_CSDIV(".plleth_lpclk", CLK_PLLETH_LPCLK, CLK_PLLETH_DIV4_LPCLK,
CSDIV0_DIVCTL2, dtable_16_128),

+ DEF_FIXED(".plldsi0_div7", CLK_PLLDSI0_DIV7, CLK_PLLDSI0, 1, 7),
+ DEF_FIXED(".plldsi1_div7", CLK_PLLDSI1_DIV7, CLK_PLLDSI1, 1, 7),
+
/* Core Clocks */
DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,
--
2.43.0