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From: Caleb James DeLisle <cjd@cjdns.fr>
To: linux-mips@vger.kernel.org
Cc: naseefkm@gmail.com, daniel.lezcano@kernel.org, tglx@kernel.org,
	robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	Caleb James DeLisle <cjd@cjdns.fr>
Subject: [PATCH 1/2] dt-bindings: timer: econet: Update EN751627 for multi-IRQ
Date: Thu, 16 Apr 2026 17:51:00 +0000	[thread overview]
Message-ID: <20260416175101.958073-2-cjd@cjdns.fr> (raw)
In-Reply-To: <20260416175101.958073-1-cjd@cjdns.fr>

From conception, this driver supported EN751627 as it is the same
hardware that is used in EN751221. However, it was expected that
EN751627 would use a percpu IRQ as does EN751221, this is how it
works in vendor code. However upon finding that the "mti,gic" intc
works on EN751627 with no modification - but it provides a unique
interrupt per-timer, it is deemed best to make this driver use
multiple IRQs when on the EN751627 platform.

Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
 .../bindings/timer/econet,en751221-timer.yaml    | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
index c1e7c2b6afde..f338739e039c 100644
--- a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
@@ -28,8 +28,8 @@ properties:
     maxItems: 2
 
   interrupts:
-    maxItems: 1
-    description: A percpu-devid timer interrupt shared across CPUs.
+    minItems: 1
+    maxItems: 4
 
   clocks:
     maxItems: 1
@@ -52,21 +52,31 @@ allOf:
           items:
             - description: VPE timers 0 and 1
             - description: VPE timers 2 and 3
+        interrupts:
+          description: An interrupt for each timer (one per VPE)
+          minItems: 4
     else:
       properties:
         reg:
           items:
             - description: VPE timers 0 and 1
+        interrupts:
+          description: A percpu-devid timer interrupt shared across timers
+          maxItems: 1
 
 additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
     timer@1fbf0400 {
         compatible = "econet,en751627-timer", "econet,en751221-timer";
         reg = <0x1fbf0400 0x100>, <0x1fbe0000 0x100>;
         interrupt-parent = <&intc>;
-        interrupts = <30>;
+        interrupts = <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>;
         clocks = <&hpt_clock>;
     };
   - |
-- 
2.39.5


  reply	other threads:[~2026-04-16 17:51 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-16 17:50 [PATCH 0/2] clocksource/timer-econet-en751221: Support irq number per timer Caleb James DeLisle
2026-04-16 17:51 ` Caleb James DeLisle [this message]
2026-04-17 16:17   ` [PATCH 1/2] dt-bindings: timer: econet: Update EN751627 for multi-IRQ Conor Dooley
2026-04-16 17:51 ` [PATCH 2/2] clocksource/timer-econet-en751221: Support irq number per timer Caleb James DeLisle

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