From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35BB5352F87; Fri, 17 Apr 2026 10:05:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776420348; cv=none; b=Ua0++PKbkewlVQZDrnjpgxGX8PLPi4EtwmD4bZr2xRFkwZ2k7BxE5IBq320iOSuLOMVnFOhO5pYOu+U8Ma+Lh1JYZy+3qJfKcG+lsbj8xvcOKJzD410A/bPHLqhZR6jY51aP+nB4WPsyvbI3P4s+etBP7/FIO+qIMD+/xODL0B0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776420348; c=relaxed/simple; bh=RB83I2nH48G2R5UVVKvA0Wx1mlrNr4P968tNH9JcDDA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qWdTg9aH3M8rNQ/dYB7wYSfEyDxbKH93zupIaQBS+wZTtQeCQS+UQN4wlShymlB8SsBOl71WKzExC/oVESqrTB6LKgUCKb67dZsWtp2jBu210oj0ZCwAPZQ3NaY5yxvRzIza3SegMHYmQqETOKGlwHhzB0rKLPxYUcEHN70zAJU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=KJL+vNEb; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="KJL+vNEb" X-UUID: fe1395463a4411f19a16598d5ca7f8ec-20260417 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Lvbv8ytIdTwjGat5iq09ZVK5234WoS7drLcT9eltSXI=; b=KJL+vNEbS673t1uDhgY6A2O8m8RKxRDupDmYmAQ3cvYnrzIm1NAyo67u+e31kzk0XdUf+dhrtd5HVuXOCHlpnoBBg1ByVSRoJBDCgTLrMc6pjZG/KEafcLjJJC6oOqHBaM1NpeFu1jMGnxuIu0fsEknHe8a5gvo654Gaxs5z/gg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:b0a69baf-1e62-4092-877c-9ad6cccc6b42,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:e7bac3a,CLOUDID:973d8a8f-6df4-4a3d-a7a4-fbdc42d669ce,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|865|888|898,TC:-5,Cont ent:0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0 ,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: fe1395463a4411f19a16598d5ca7f8ec-20260417 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 405505398; Fri, 17 Apr 2026 18:05:42 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 17 Apr 2026 18:05:40 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 17 Apr 2026 18:05:39 +0800 From: Jianhua Lin To: , , , , , , CC: , , , , , , , , , Jianhua Lin Subject: [PATCH v7 3/3] media: mediatek: jpeg: add compatible for MT8189 SoC Date: Fri, 17 Apr 2026 18:05:19 +0800 Message-ID: <20260417100519.1043-4-jianhua.lin@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260417100519.1043-1-jianhua.lin@mediatek.com> References: <20260417100519.1043-1-jianhua.lin@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Compared to the previous generation ICs, the MT8189 uses a 34-bit IOVA address space (16GB) and requires a single clock configuration. Therefore, add new compatible strings ("mediatek,mt8189-jpgenc" and "mediatek,mt8189-jpgdec") along with their specific driver data to support the JPEG encoder and decoder of the MT8189 SoC. Signed-off-by: Jianhua Lin --- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c index 8c684756d5fc..786cc2942c3a 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -1867,6 +1867,10 @@ static struct clk_bulk_data mt8173_jpeg_dec_clocks[] = { { .id = "jpgdec" }, }; +static struct clk_bulk_data mtk_jpeg_dec_clocks[] = { + { .id = "jpgdec" }, +}; + static const struct mtk_jpeg_variant mt8173_jpeg_drvdata = { .clks = mt8173_jpeg_dec_clocks, .num_clks = ARRAY_SIZE(mt8173_jpeg_dec_clocks), @@ -1898,6 +1902,38 @@ static const struct mtk_jpeg_variant mtk_jpeg_drvdata = { .multi_core = false, }; +static const struct mtk_jpeg_variant mtk8189_jpegenc_drvdata = { + .clks = mtk_jpeg_clocks, + .num_clks = ARRAY_SIZE(mtk_jpeg_clocks), + .formats = mtk_jpeg_enc_formats, + .num_formats = MTK_JPEG_ENC_NUM_FORMATS, + .qops = &mtk_jpeg_enc_qops, + .irq_handler = mtk_jpeg_enc_irq, + .hw_reset = mtk_jpeg_enc_reset, + .m2m_ops = &mtk_jpeg_enc_m2m_ops, + .dev_name = "mtk-jpeg-enc", + .ioctl_ops = &mtk_jpeg_enc_ioctl_ops, + .out_q_default_fourcc = V4L2_PIX_FMT_YUYV, + .cap_q_default_fourcc = V4L2_PIX_FMT_JPEG, + .support_34bit = true, +}; + +static const struct mtk_jpeg_variant mtk8189_jpegdec_drvdata = { + .clks = mtk_jpeg_dec_clocks, + .num_clks = ARRAY_SIZE(mtk_jpeg_dec_clocks), + .formats = mtk_jpeg_dec_formats, + .num_formats = MTK_JPEG_DEC_NUM_FORMATS, + .qops = &mtk_jpeg_dec_qops, + .irq_handler = mtk_jpeg_dec_irq, + .hw_reset = mtk_jpeg_dec_reset, + .m2m_ops = &mtk_jpeg_dec_m2m_ops, + .dev_name = "mtk-jpeg-dec", + .ioctl_ops = &mtk_jpeg_dec_ioctl_ops, + .out_q_default_fourcc = V4L2_PIX_FMT_JPEG, + .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M, + .support_34bit = true, +}; + static struct mtk_jpeg_variant mtk8195_jpegenc_drvdata = { .formats = mtk_jpeg_enc_formats, .num_formats = MTK_JPEG_ENC_NUM_FORMATS, @@ -1937,6 +1973,14 @@ static const struct of_device_id mtk_jpeg_match[] = { .compatible = "mediatek,mtk-jpgenc", .data = &mtk_jpeg_drvdata, }, + { + .compatible = "mediatek,mt8189-jpgenc", + .data = &mtk8189_jpegenc_drvdata, + }, + { + .compatible = "mediatek,mt8189-jpgdec", + .data = &mtk8189_jpegdec_drvdata, + }, { .compatible = "mediatek,mt8195-jpgenc", .data = &mtk8195_jpegenc_drvdata, -- 2.45.2