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[104.155.83.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488fb72d365sm144280285e9.1.2026.04.20.10.40.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2026 10:40:10 -0700 (PDT) From: Tudor Ambarus Date: Mon, 20 Apr 2026 17:39:55 +0000 Subject: [PATCH v3 09/10] arm64: dts: exynos: gs101: Add thermal management unit Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260420-acpm-tmu-v3-9-3dc8e93f0b26@linaro.org> References: <20260420-acpm-tmu-v3-0-3dc8e93f0b26@linaro.org> In-Reply-To: <20260420-acpm-tmu-v3-0-3dc8e93f0b26@linaro.org> To: "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Daniel Lezcano , Sylwester Nawrocki , Chanwoo Choi , Michael Turquette , Stephen Boyd , Lee Jones Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, linux-clk@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776706804; l=7069; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=9sh57TDQqH/7ssKytowavLn5M99k4zWI7dQ0wDDuyzs=; b=ybbkW7PAs2lzi9awopvn2/X2xHSJ6YJT1i3T0gkdLZZ+pvHOa8zy1doChcGdyRHJtX4WYwGID J5+CdT4WPqnB1flSAgTxcc6QZWjZ15yHZmK4HXe+Vcge6sApgsbgRZS X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the Thermal Management Unit (TMU) support for the Google GS101 SoC. Describe the TMU using a consolidated SoC node that includes memory resources for interrupt identification and a phandle to the ACPM IPC interface for functional control. Define thermal zones for the little, mid, and big CPU clusters, including associated trip points and cooling-device maps to enable thermal mitigation. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi | 136 +++++++++++++++++++++++ arch/arm64/boot/dts/exynos/google/gs101.dtsi | 18 +++ 2 files changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi new file mode 100644 index 000000000000..b27d1a539ec2 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS101 TMU configurations device tree source + * + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include + +/ { + thermal-zones { + cpucl2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 0>; + + trips { + big_switch_on: big-switch-on { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + big_mitigate: big-mitigate { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + big_hot: big-hot { + temperature = <100000>; + hysteresis = <5000>; + type = "hot"; + }; + + big_critical: big-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&big_mitigate>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 1>; + + trips { + mid_switch_on: mid-switch-on { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + mid_mitigate: mid-mitigate { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + mid_hot: mid-hot { + temperature = <100000>; + hysteresis = <5000>; + type = "hot"; + }; + + mid_critical: mid-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&mid_mitigate>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 2>; + + trips { + little_switch_on: little-switch-on { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + little_mitigate: little-mitigate { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + little_hot: little-hot { + temperature = <100000>; + hysteresis = <5000>; + type = "hot"; + }; + + little_critical: little-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&little_mitigate>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index d085f9fb0f62..4b8c7edaddb6 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -74,6 +74,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0x0000>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -86,6 +87,7 @@ cpu1: cpu@100 { compatible = "arm,cortex-a55"; reg = <0x0100>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -98,6 +100,7 @@ cpu2: cpu@200 { compatible = "arm,cortex-a55"; reg = <0x0200>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -110,6 +113,7 @@ cpu3: cpu@300 { compatible = "arm,cortex-a55"; reg = <0x0300>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; @@ -122,6 +126,7 @@ cpu4: cpu@400 { compatible = "arm,cortex-a76"; reg = <0x0400>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; @@ -134,6 +139,7 @@ cpu5: cpu@500 { compatible = "arm,cortex-a76"; reg = <0x0500>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; @@ -146,6 +152,7 @@ cpu6: cpu@600 { compatible = "arm,cortex-x1"; reg = <0x0600>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; @@ -158,6 +165,7 @@ cpu7: cpu@700 { compatible = "arm,cortex-x1"; reg = <0x0700>; clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells = <2>; enable-method = "psci"; cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; @@ -639,6 +647,15 @@ watchdog_cl1: watchdog@10070000 { status = "disabled"; }; + tmu_top: thermal-sensor@100a0000 { + compatible = "google,gs101-tmu-top"; + reg = <0x100a0000 0x800>; + clocks = <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; + interrupts = ; + samsung,acpm-ipc = <&acpm_ipc>; + #thermal-sensor-cells = <1>; + }; + trng: rng@10141400 { compatible = "google,gs101-trng", "samsung,exynos850-trng"; @@ -1861,3 +1878,4 @@ timer { }; #include "gs101-pinctrl.dtsi" +#include "gs101-tmu.dtsi" -- 2.54.0.rc1.555.g9c883467ad-goog