From: Conor Dooley <conor@kernel.org>
To: Biju <biju.das.au@gmail.com>
Cc: Lee Jones <lee@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Subject: Re: [PATCH 1/3] dt-bindings: mfd: syscon: Document the LVDS_CMN syscon for the RZ/G3L
Date: Mon, 20 Apr 2026 17:21:55 +0100 [thread overview]
Message-ID: <20260420-carry-freefall-c4ab36009cab@spud> (raw)
In-Reply-To: <20260417175235.224809-2-biju.das.jz@bp.renesas.com>
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On Fri, Apr 17, 2026 at 06:52:28PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> The RZ/G3{E,L} SoCs have an LVDS Common (LVDS_CMN) region which is common
> to all LVDS channels. The RZ/G3L has single-link, but the RZ/G3E has both
> single and dual-link.
>
> Use the syscon interface to access these registers for scalability.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
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next prev parent reply other threads:[~2026-04-20 16:22 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-17 17:52 [PATCH 0/3] Add support for Renesas RZ/G3L LVDS encoder Biju
2026-04-17 17:52 ` [PATCH 1/3] dt-bindings: mfd: syscon: Document the LVDS_CMN syscon for the RZ/G3L Biju
2026-04-20 16:21 ` Conor Dooley [this message]
2026-04-17 17:52 ` [PATCH 2/3] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder Biju
2026-04-20 16:21 ` Conor Dooley
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