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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12c74a20c55sm13056111c88.13.2026.04.19.20.52.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Apr 2026 20:52:06 -0700 (PDT) From: Shawn Guo To: Jassi Brar Cc: Sibi Sankar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Shawn Guo Subject: [PATCH 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC Date: Mon, 20 Apr 2026 11:49:30 +0800 Message-ID: <20260420034932.1247344-1-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIwMDAzMyBTYWx0ZWRfXwq3jmbpQ0CV4 DrqZASNZSocRlNuRORlbC3LxuSnQ3axAysppersoeh5O9co96JZ5FyMM1JaEC63ssk8wheJyXT/ XBULEa0M3hwyR89SuGgG4XTMdMz3DaYi7gvP/CR6R4tP29gmyU7SBE3VE5upN6Qf1W2f3sSTDVE TthQrdgoeswHFBi3IrvI19ra6zdOYCgGhqeJeHAmM5sKN1oTwQWeK3nH+FY13909ctEc231uAYY uU943V2ye+zp1hMIKfo/rwoGQnMeAJH1O88jZXBUpujAvbI/PFWE1NiOWQdtljV/+wCe/zKXkdi 8Cb9VYyzdcLERMFsnjjhukO/vhGYKMU+fH+sj+848NBFf0hWHfDmQ93lyqh55ZwPxnljS0goEeQ gcb2jDJvST9FomBM4T5P6Qie3PDYPw9JGqbwjKPWoneLPVTSjy01pxpX/t5fFuFvITTEAfTLjeP 1CwT/03quFlUs0iG1bA== X-Proofpoint-GUID: vE11L5LSOTVHe1eA1PNr8t5x9tXjLtw5 X-Proofpoint-ORIG-GUID: vE11L5LSOTVHe1eA1PNr8t5x9tXjLtw5 X-Authority-Analysis: v=2.4 cv=WK1PmHsR c=1 sm=1 tr=0 ts=69e5a2e9 cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=rxKuTeQDrr0-oB1YhZwA:9 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-19_07,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 spamscore=0 malwarescore=0 bulkscore=0 suspectscore=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604200033 This series adds CPUCP mailbox controller support for Qualcomm Nord SoC. The Nord CPUCP mailbox is functionally identical to the existing x1e80100 implementation, except it exposes 16 IPC channels instead of 3. Patch 1 adds the Nord compatible string to the DT binding. Patch 2 refactors the channel count from a hardcoded compile-time constant into a per-hardware configuration struct populated via the device tree match data. Deepti Jaggi (2): dt-bindings: mailbox: qcom: Document Nord CPUCP mailbox controller mailbox: qcom-cpucp: Add support for Nord CPUCP mailbox controller .../bindings/mailbox/qcom,cpucp-mbox.yaml | 1 + drivers/mailbox/qcom-cpucp-mbox.c | 37 ++++++++++++++++--- 2 files changed, 32 insertions(+), 6 deletions(-) -- 2.43.0